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Marc Jones2006b382007-12-19 00:47:09 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Carl-Daniel Hailfingerf2ecb742008-01-08 17:28:35 +00003 *
Marc Jones2006b382007-12-19 00:47:09 +00004 * Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +00005 * Copyright (C) 2008 Carl-Daniel Hailfinger
Marc Jones2006b382007-12-19 00:47:09 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Carl-Daniel Hailfingerf2ecb742008-01-08 17:28:35 +000019 */
20
arch import user (historical)6ca76362005-07-06 17:17:25 +000021#include <cpu/x86/mtrr.h>
22#include <cpu/amd/mtrr.h>
Uwe Hermann42926842010-09-30 23:15:36 +000023
24#define CacheSize CONFIG_DCACHE_RAM_SIZE
25#define CacheBase (0xd0000 - CacheSize)
26
27/* Leave some space for global variable to pass to RAM stage. */
28#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
29
30/* For CAR with Fam10h. */
31#define CacheSizeAPStack 0x400 /* 1K */
32
33#define MSR_MCFG_BASE 0xC0010058
34#define MSR_FAM10 0xC001102A
35
36#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
37
38#define CPUID_MASK 0x0ff00f00
39#define CPUID_VAL_FAM10_ROTATED 0x0f000010
40
Patrick Georgi08afc6d2009-02-17 12:56:58 +000041/*
Stefan Reinauer6f57b512010-07-08 16:41:05 +000042 * XMM map:
Uwe Hermann42926842010-09-30 23:15:36 +000043 * xmm1: CPU family
44 * xmm2: Fam10h comparison value
45 * xmm3: Backup EBX
Stefan Reinauer6f57b512010-07-08 16:41:05 +000046 */
arch import user (historical)6ca76362005-07-06 17:17:25 +000047
Stefan Reinauer7b0500c2011-01-19 06:54:42 +000048 /* Save the BIST result. */
49 movl %eax, %ebp
Marc Jones2006b382007-12-19 00:47:09 +000050
Uwe Hermann42926842010-09-30 23:15:36 +000051 /*
52 * For normal part %ebx already contain cpu_init_detected
53 * from fallback call.
54 */
arch import user (historical)6ca76362005-07-06 17:17:25 +000055
Stefan Reinauer806e1462005-12-01 10:54:44 +000056cache_as_ram_setup:
Stefan Reinaueraed99202010-06-07 08:29:36 +000057 post_code(0xa0)
Yinghai Lu6f63c022005-12-14 20:08:23 +000058
Stefan Reinauer7b0500c2011-01-19 06:54:42 +000059 /* Enable SSE. */
60 movl %cr4, %eax
61 orl $(3 << 9), %eax
62 movl %eax, %cr4
Patrick Georgi08afc6d2009-02-17 12:56:58 +000063
Uwe Hermann42926842010-09-30 23:15:36 +000064 /* Figure out the CPU family. */
Patrick Georgi08afc6d2009-02-17 12:56:58 +000065 cvtsi2sd %ebx, %xmm3
66 movl $0x01, %eax
67 cpuid
Uwe Hermann42926842010-09-30 23:15:36 +000068 /* Base family is bits 8..11, extended family is bits 20..27. */
Patrick Georgi08afc6d2009-02-17 12:56:58 +000069 andl $CPUID_MASK, %eax
Uwe Hermann42926842010-09-30 23:15:36 +000070 /* Reorder bits for easier comparison by value. */
Patrick Georgi08afc6d2009-02-17 12:56:58 +000071 roll $0x10, %eax
72 cvtsi2sd %eax, %xmm1
73 movl $CPUID_VAL_FAM10_ROTATED, %eax
74 cvtsi2sd %eax, %xmm2
75 cvtsd2si %xmm3, %ebx
76
Uwe Hermann42926842010-09-30 23:15:36 +000077 /* Check if cpu_init_detected. */
Ronald G. Minnichfb0a64b2005-11-23 21:01:08 +000078 movl $MTRRdefType_MSR, %ecx
79 rdmsr
Stefan Reinauer139e6f92011-04-14 20:06:30 +000080 andl $MTRRdefTypeEn, %eax
Uwe Hermann42926842010-09-30 23:15:36 +000081 movl %eax, %ebx /* We store the status. */
Marc Jones2006b382007-12-19 00:47:09 +000082
Patrick Georgi08afc6d2009-02-17 12:56:58 +000083 jmp_if_k8(CAR_FAM10_out_post_errata)
84
Uwe Hermann42926842010-09-30 23:15:36 +000085 /*
86 * For GH, CAR need to set DRAM Base/Limit registers to direct that
87 * to node0.
88 * Only BSP needed, for other nodes set during HT/memory init.
89 * So we need to check if it is BSP.
90 */
Marc Jones8ae8c882007-12-19 01:32:08 +000091 movl $0x1b, %ecx
92 rdmsr
Uwe Hermann66d16872010-10-01 07:27:51 +000093 bt $8, %eax /* BSP */
Marc Jones8ae8c882007-12-19 01:32:08 +000094 jnc CAR_FAM10_out
95
Uwe Hermann42926842010-09-30 23:15:36 +000096 /* Enable RT tables on BSP. */
Marc Jones8ae8c882007-12-19 01:32:08 +000097 movl $0x8000c06c, %eax
98 movw $0xcf8, %dx
99 outl %eax, %dx
100 addw $4, %dx
101 inl %dx, %eax
102 btr $0, %eax
103 outl %eax, %dx
104
Uwe Hermann42926842010-09-30 23:15:36 +0000105 /* Setup temporary DRAM map: [0,16M) bit 0-23. */
Marc Jones8ae8c882007-12-19 01:32:08 +0000106 movl $0x8000c144, %eax
107 movw $0xcf8, %dx
108 outl %eax, %dx
109 addw $4, %dx
110 movl $0, %eax
111 outl %eax, %dx
112
113 movl $0x8000c140, %eax
114 movw $0xcf8, %dx
115 outl %eax, %dx
116 addw $4, %dx
117 movl $3, %eax
118 outl %eax, %dx
119
120CAR_FAM10_out:
121
Uwe Hermann42926842010-09-30 23:15:36 +0000122 /*
123 * Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
124 * Re-enable it in after RAM is initialized and before CAR is disabled.
Stefan Reinauer6f57b512010-07-08 16:41:05 +0000125 */
Arne Georg Gleditsche7a5b762010-09-13 15:11:35 +0000126 movl $MSR_FAM10, %ecx
Marc Jones8ae8c882007-12-19 01:32:08 +0000127 rdmsr
128 bts $15, %eax
129 wrmsr
Patrick Georgi08afc6d2009-02-17 12:56:58 +0000130
Marco Schmidtc263b442009-06-06 11:21:52 +0000131 /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
Myles Watson707fad02009-10-23 18:22:27 +0000132 movl $MSR_FAM10, %ecx
Marco Schmidtc263b442009-06-06 11:21:52 +0000133 rdmsr
Uwe Hermann42926842010-09-30 23:15:36 +0000134 bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */
Marco Schmidtc263b442009-06-06 11:21:52 +0000135 wrmsr
136
Myles Watson2b286142010-09-13 17:46:13 +0000137#if CONFIG_MMCONF_SUPPORT
Scott Duplichanbda153b2010-10-19 21:08:11 +0000138 #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
139 #error "MMCONF_BASE_ADDRESS too big"
140 #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
141 #error "MMCONF_BASE_ADDRESS not 1MB aligned"
142 #endif
143 movl $0, %edx
144 movl $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax
145 #if (CONFIG_MMCONF_BUS_NUMBER == 1)
146 #elif (CONFIG_MMCONF_BUS_NUMBER == 2)
147 orl $(1 << 2), %eax
148 #elif (CONFIG_MMCONF_BUS_NUMBER == 4)
149 orl $(2 << 2), %eax
150 #elif (CONFIG_MMCONF_BUS_NUMBER == 8)
151 orl $(3 << 2), %eax
152 #elif (CONFIG_MMCONF_BUS_NUMBER == 16)
153 orl $(4 << 2), %eax
154 #elif (CONFIG_MMCONF_BUS_NUMBER == 32)
155 orl $(5 << 2), %eax
156 #elif (CONFIG_MMCONF_BUS_NUMBER == 64)
157 orl $(6 << 2), %eax
158 #elif (CONFIG_MMCONF_BUS_NUMBER == 128)
159 orl $(7 << 2), %eax
160 #elif (CONFIG_MMCONF_BUS_NUMBER == 256)
161 orl $(8 << 2), %eax
162 #else
163 #error "bad MMCONF_BUS_NUMBER value"
164 #endif
165 movl $(0xc0010058), %ecx
Arne Georg Gleditsche7a5b762010-09-13 15:11:35 +0000166 wrmsr
167#endif
168
Patrick Georgi08afc6d2009-02-17 12:56:58 +0000169CAR_FAM10_out_post_errata:
Marc Jones8ae8c882007-12-19 01:32:08 +0000170
Uwe Hermann42926842010-09-30 23:15:36 +0000171 /* Set MtrrFixDramModEn for clear fixed MTRR. */
arch import user (historical)6ca76362005-07-06 17:17:25 +0000172enable_fixed_mtrr_dram_modify:
173 movl $SYSCFG_MSR, %ecx
174 rdmsr
Marc Jones2006b382007-12-19 00:47:09 +0000175 andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax
arch import user (historical)6ca76362005-07-06 17:17:25 +0000176 orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
177 wrmsr
178
Uwe Hermann42926842010-09-30 23:15:36 +0000179 /* Clear all MTRRs. */
Marc Jones2006b382007-12-19 00:47:09 +0000180 xorl %edx, %edx
Warren Turkal4ffde942010-10-12 06:13:40 +0000181 movl $all_mtrr_msrs, %esi
Carl-Daniel Hailfingerf2ecb742008-01-08 17:28:35 +0000182
arch import user (historical)6ca76362005-07-06 17:17:25 +0000183clear_fixed_var_mtrr:
Marc Jones2006b382007-12-19 00:47:09 +0000184 lodsl (%esi), %eax
185 testl %eax, %eax
Myles Watson707fad02009-10-23 18:22:27 +0000186 jz clear_fixed_var_mtrr_out
arch import user (historical)6ca76362005-07-06 17:17:25 +0000187
Marc Jones2006b382007-12-19 00:47:09 +0000188 movl %eax, %ecx
189 xorl %eax, %eax
190 wrmsr
arch import user (historical)6ca76362005-07-06 17:17:25 +0000191
Myles Watson707fad02009-10-23 18:22:27 +0000192 jmp clear_fixed_var_mtrr
arch import user (historical)6ca76362005-07-06 17:17:25 +0000193clear_fixed_var_mtrr_out:
194
Uwe Hermann42926842010-09-30 23:15:36 +0000195/*
196 * 0x06 is the WB IO type for a given 4k segment.
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000197 * 0x1e is the MEM IO type for a given 4k segment (K10 and above).
198 * segs is the number of 4k segments in the area of the particular
Uwe Hermann42926842010-09-30 23:15:36 +0000199 * register we want to use for CAR.
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000200 * reg is the register where the IO type should be stored.
201 */
202.macro extractmask segs, reg
203.if \segs <= 0
Uwe Hermann42926842010-09-30 23:15:36 +0000204 /*
205 * The xorl here is superfluous because at the point of first execution
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000206 * of this macro, %eax and %edx are cleared. Later invocations of this
207 * macro will have a monotonically increasing segs parameter.
208 */
Uwe Hermann42926842010-09-30 23:15:36 +0000209 xorl \reg, \reg
Patrick Georgi08afc6d2009-02-17 12:56:58 +0000210.else
211 jmp_if_k8(1f)
212
213.if \segs == 1
Uwe Hermann42926842010-09-30 23:15:36 +0000214 movl $0x1e000000, \reg /* WB MEM type */
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000215.elseif \segs == 2
Uwe Hermann42926842010-09-30 23:15:36 +0000216 movl $0x1e1e0000, \reg /* WB MEM type */
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000217.elseif \segs == 3
Uwe Hermann42926842010-09-30 23:15:36 +0000218 movl $0x1e1e1e00, \reg /* WB MEM type */
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000219.elseif \segs >= 4
Uwe Hermann42926842010-09-30 23:15:36 +0000220 movl $0x1e1e1e1e, \reg /* WB MEM type */
Patrick Georgi08afc6d2009-02-17 12:56:58 +0000221.endif
222 jmp 2f
2231:
224.if \segs == 1
Uwe Hermann42926842010-09-30 23:15:36 +0000225 movl $0x06000000, \reg /* WB IO type */
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000226.elseif \segs == 2
Uwe Hermann42926842010-09-30 23:15:36 +0000227 movl $0x06060000, \reg /* WB IO type */
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000228.elseif \segs == 3
Uwe Hermann42926842010-09-30 23:15:36 +0000229 movl $0x06060600, \reg /* WB IO type */
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000230.elseif \segs >= 4
Uwe Hermann42926842010-09-30 23:15:36 +0000231 movl $0x06060606, \reg /* WB IO type */
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000232.endif
Patrick Georgi08afc6d2009-02-17 12:56:58 +00002332:
234.endif /* if \segs <= 0 */
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000235.endm
Marc Jones8ae8c882007-12-19 01:32:08 +0000236
Uwe Hermann42926842010-09-30 23:15:36 +0000237/*
Uwe Hermann66d16872010-10-01 07:27:51 +0000238 * carsize is the cache size in bytes we want to use for CAR.
Uwe Hermann42926842010-09-30 23:15:36 +0000239 * windowoffset is the 32k-aligned window into CAR size.
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000240 */
241.macro simplemask carsize, windowoffset
Carl-Daniel Hailfingered8dc582008-01-10 17:59:25 +0000242 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
243 extractmask gas_bug_workaround, %eax
244 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
245 extractmask gas_bug_workaround, %edx
Uwe Hermann42926842010-09-30 23:15:36 +0000246 /*
247 * Without the gas bug workaround, the entire macro would consist
248 * only of the two lines below:
249 * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
250 * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
251 */
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000252.endm
253
254#if CacheSize > 0x10000
255#error Invalid CAR size, must be at most 64k.
256#endif
257#if CacheSize < 0x1000
258#error Invalid CAR size, must be at least 4k. This is a processor limitation.
259#endif
260#if (CacheSize & (0x1000 - 1))
261#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
Yinghai Lud4b278c2006-10-04 20:46:15 +0000262#endif
arch import user (historical)6ca76362005-07-06 17:17:25 +0000263
Myles Watson707fad02009-10-23 18:22:27 +0000264#if CacheSize > 0x8000
Uwe Hermann42926842010-09-30 23:15:36 +0000265 /* Enable caching for 32K-64K using fixed MTRR. */
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000266 movl $MTRRfix4K_C0000_MSR, %ecx
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000267 simplemask CacheSize, 0x8000
Myles Watson707fad02009-10-23 18:22:27 +0000268 wrmsr
Yinghai Lud4b278c2006-10-04 20:46:15 +0000269#endif
270
Uwe Hermann42926842010-09-30 23:15:36 +0000271 /* Enable caching for 0-32K using fixed MTRR. */
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000272 movl $MTRRfix4K_C8000_MSR, %ecx
Carl-Daniel Hailfinger1923fc42008-01-10 17:48:25 +0000273 simplemask CacheSize, 0
arch import user (historical)6ca76362005-07-06 17:17:25 +0000274 wrmsr
Yinghai Lu6f63c022005-12-14 20:08:23 +0000275
Uwe Hermann42926842010-09-30 23:15:36 +0000276 /* Enable memory access for first MBs using top_mem. */
Marc Jones2006b382007-12-19 00:47:09 +0000277 movl $TOP_MEM, %ecx
278 xorl %edx, %edx
Myles Watson0f61a4f2009-10-16 16:32:57 +0000279 movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
Marc Jones2006b382007-12-19 00:47:09 +0000280 wrmsr
Yinghai Lu6f63c022005-12-14 20:08:23 +0000281
Stefan Reinauer08670622009-06-30 15:17:49 +0000282#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
Rudolf Marek95c50c62010-01-05 17:35:44 +0000283
Uwe Hermann42926842010-09-30 23:15:36 +0000284 /* Enable write base caching so we can do execute in place (XIP)
285 * on the flash ROM.
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000286 */
287 movl $MTRRphysBase_MSR(1), %ecx
288 xorl %edx, %edx
Uwe Hermann36455aa2010-10-02 20:51:29 +0000289 /*
Patrick Georgi1da10462011-10-28 20:28:03 +0200290 * IMPORTANT: The following calculation _must_ be done at runtime. See
Uwe Hermann36455aa2010-10-02 20:51:29 +0000291 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
292 */
Patrick Georgi1da10462011-10-28 20:28:03 +0200293 movl copy_and_run, %eax
294 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
295 orl $MTRR_TYPE_WRBACK, %eax
Marc Jones2006b382007-12-19 00:47:09 +0000296 wrmsr
arch import user (historical)6ca76362005-07-06 17:17:25 +0000297
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000298 movl $MTRRphysMask_MSR(1), %ecx
Stefan Reinauer08670622009-06-30 15:17:49 +0000299 movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
Patrick Georgi08afc6d2009-02-17 12:56:58 +0000300 jmp_if_k8(wbcache_post_fam10_setup)
Stefan Reinauer08670622009-06-30 15:17:49 +0000301 movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
Patrick Georgi08afc6d2009-02-17 12:56:58 +0000302wbcache_post_fam10_setup:
Stefan Reinauer139e6f92011-04-14 20:06:30 +0000303 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
Marc Jones2006b382007-12-19 00:47:09 +0000304 wrmsr
Stefan Reinauer08670622009-06-30 15:17:49 +0000305#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
arch import user (historical)6ca76362005-07-06 17:17:25 +0000306
Uwe Hermann42926842010-09-30 23:15:36 +0000307 /* Set the default memory type and enable fixed and variable MTRRs. */
Marc Jones2006b382007-12-19 00:47:09 +0000308 movl $MTRRdefType_MSR, %ecx
309 xorl %edx, %edx
Uwe Hermann66d16872010-10-01 07:27:51 +0000310 movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
Marc Jones2006b382007-12-19 00:47:09 +0000311 wrmsr
312
Uwe Hermann42926842010-09-30 23:15:36 +0000313 /* Enable the MTRRs and IORRs in SYSCFG. */
Marc Jones2006b382007-12-19 00:47:09 +0000314 movl $SYSCFG_MSR, %ecx
315 rdmsr
Myles Watson707fad02009-10-23 18:22:27 +0000316 orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
Marc Jones2006b382007-12-19 00:47:09 +0000317 wrmsr
Marc Jones2006b382007-12-19 00:47:09 +0000318
Stefan Reinaueraed99202010-06-07 08:29:36 +0000319 post_code(0xa1)
Carl-Daniel Hailfingerf2ecb742008-01-08 17:28:35 +0000320
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000321 /* Enable cache. */
322 movl %cr0, %eax
323 andl $(~((1 << 30) | (1 << 29))), %eax
324 movl %eax, %cr0
Marc Jones2006b382007-12-19 00:47:09 +0000325
Patrick Georgi08afc6d2009-02-17 12:56:58 +0000326 jmp_if_k8(fam10_end_part1)
327
Uwe Hermann42926842010-09-30 23:15:36 +0000328 /* So we need to check if it is BSP. */
Marc Jones8ae8c882007-12-19 01:32:08 +0000329 movl $0x1b, %ecx
330 rdmsr
Uwe Hermann66d16872010-10-01 07:27:51 +0000331 bt $8, %eax /* BSP */
Marc Jones8ae8c882007-12-19 01:32:08 +0000332 jnc CAR_FAM10_ap
Patrick Georgi08afc6d2009-02-17 12:56:58 +0000333fam10_end_part1:
Carl-Daniel Hailfingerf2ecb742008-01-08 17:28:35 +0000334
Stefan Reinaueraed99202010-06-07 08:29:36 +0000335 post_code(0xa2)
Marc Jones8ae8c882007-12-19 01:32:08 +0000336
Uwe Hermann42926842010-09-30 23:15:36 +0000337 /* Read the range with lodsl. */
Yinghai Lu6f63c022005-12-14 20:08:23 +0000338 cld
Marc Jones2006b382007-12-19 00:47:09 +0000339 movl $CacheBase, %esi
340 movl $(CacheSize >> 2), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000341 rep lodsl
342
Uwe Hermann42926842010-09-30 23:15:36 +0000343 /* Clear the range. */
Marc Jones2006b382007-12-19 00:47:09 +0000344 movl $CacheBase, %edi
345 movl $(CacheSize >> 2), %ecx
346 xorl %eax, %eax
Myles Watson707fad02009-10-23 18:22:27 +0000347 rep stosl
arch import user (historical)6ca76362005-07-06 17:17:25 +0000348
Uwe Hermann42926842010-09-30 23:15:36 +0000349 /* Set up the stack pointer. */
Marc Jones2006b382007-12-19 00:47:09 +0000350 movl $(CacheBase + CacheSize - GlobalVarSize), %eax
351 movl %eax, %esp
Carl-Daniel Hailfingerf2ecb742008-01-08 17:28:35 +0000352
Stefan Reinaueraed99202010-06-07 08:29:36 +0000353 post_code(0xa3)
Marc Jones8ae8c882007-12-19 01:32:08 +0000354
Marc Jones8ae8c882007-12-19 01:32:08 +0000355 jmp CAR_FAM10_ap_out
356CAR_FAM10_ap:
Uwe Hermann42926842010-09-30 23:15:36 +0000357 /*
358 * Need to set stack pointer for AP.
359 * It will be from:
360 * CacheBase + (CacheSize - GlobalVarSize) / 2
361 * - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack
362 * So need to get the NodeID and CoreID at first.
363 * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need
364 * to reverse it.
365 */
Marc Jones8ae8c882007-12-19 01:32:08 +0000366
Uwe Hermann42926842010-09-30 23:15:36 +0000367 /* Store our init detected. */
Marc Jones8ae8c882007-12-19 01:32:08 +0000368 movl %ebx, %esi
369
Uwe Hermann42926842010-09-30 23:15:36 +0000370 /* Get the coreid bits at first. */
Marc Jones8ae8c882007-12-19 01:32:08 +0000371 movl $0x80000008, %eax
372 cpuid
373 shrl $12, %ecx
374 andl $0x0f, %ecx
375 movl %ecx, %edi
376
Uwe Hermann42926842010-09-30 23:15:36 +0000377 /* Get the initial APIC ID. */
Marc Jones8ae8c882007-12-19 01:32:08 +0000378 movl $1, %eax
379 cpuid
380 shrl $24, %ebx
381
Uwe Hermann42926842010-09-30 23:15:36 +0000382 /* Get the nb cfg bit 54. */
383 movl $0xc001001f, %ecx /* NB_CFG_MSR */
Marc Jones8ae8c882007-12-19 01:32:08 +0000384 rdmsr
Uwe Hermann42926842010-09-30 23:15:36 +0000385 movl %edi, %ecx /* CoreID bits */
Uwe Hermann66d16872010-10-01 07:27:51 +0000386 bt $(54 - 32), %edx
Marc Jones8ae8c882007-12-19 01:32:08 +0000387 jc roll_cfg
388 rolb %cl, %bl
389roll_cfg:
Carl-Daniel Hailfingerf2ecb742008-01-08 17:28:35 +0000390
Uwe Hermann42926842010-09-30 23:15:36 +0000391 /* Calculate stack pointer. */
Marc Jones8ae8c882007-12-19 01:32:08 +0000392 movl $CacheSizeAPStack, %eax
393 mull %ebx
Uwe Hermann42926842010-09-30 23:15:36 +0000394 movl $(CacheBase + (CacheSize - GlobalVarSize) / 2), %esp
Marc Jones8ae8c882007-12-19 01:32:08 +0000395 subl %eax, %esp
396
Uwe Hermann42926842010-09-30 23:15:36 +0000397 /* Retrive init detected. */
Marc Jones8ae8c882007-12-19 01:32:08 +0000398 movl %esi, %ebx
399
Stefan Reinaueraed99202010-06-07 08:29:36 +0000400 post_code(0xa4)
Marc Jones8ae8c882007-12-19 01:32:08 +0000401
402CAR_FAM10_ap_out:
Marc Jones8ae8c882007-12-19 01:32:08 +0000403
Stefan Reinaueraed99202010-06-07 08:29:36 +0000404 post_code(0xa5)
arch import user (historical)6ca76362005-07-06 17:17:25 +0000405
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000406 /* Disable SSE. */
407 movl %cr4, %eax
408 andl $~(3 << 9), %eax
409 movl %eax, %cr4
Patrick Georgi08afc6d2009-02-17 12:56:58 +0000410
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000411 /* Restore the BIST result. */
412 movl %ebp, %eax
Carl-Daniel Hailfingerf2ecb742008-01-08 17:28:35 +0000413
Uwe Hermann42926842010-09-30 23:15:36 +0000414 /* We need to set EBP? No need. */
arch import user (historical)6ca76362005-07-06 17:17:25 +0000415 movl %esp, %ebp
Uwe Hermann42926842010-09-30 23:15:36 +0000416 pushl %ebx /* Init detected. */
417 pushl %eax /* BIST */
Marc Jones2006b382007-12-19 00:47:09 +0000418 call cache_as_ram_main
Uwe Hermann42926842010-09-30 23:15:36 +0000419 /* We will not go back. */
arch import user (historical)6ca76362005-07-06 17:17:25 +0000420
Uwe Hermann42926842010-09-30 23:15:36 +0000421 post_code(0xaf) /* Should never see this POST code. */
Marc Jones8ae8c882007-12-19 01:32:08 +0000422
Warren Turkal4ffde942010-10-12 06:13:40 +0000423all_mtrr_msrs:
424 /* fixed MTRR MSRs */
425 .long MTRRfix64K_00000_MSR
426 .long MTRRfix16K_80000_MSR
427 .long MTRRfix16K_A0000_MSR
428 .long MTRRfix4K_C0000_MSR
429 .long MTRRfix4K_C8000_MSR
430 .long MTRRfix4K_D0000_MSR
431 .long MTRRfix4K_D8000_MSR
432 .long MTRRfix4K_E0000_MSR
433 .long MTRRfix4K_E8000_MSR
434 .long MTRRfix4K_F0000_MSR
435 .long MTRRfix4K_F8000_MSR
Uwe Hermann42926842010-09-30 23:15:36 +0000436
Warren Turkal4ffde942010-10-12 06:13:40 +0000437 /* var MTRR MSRs */
438 .long MTRRphysBase_MSR(0)
439 .long MTRRphysMask_MSR(0)
440 .long MTRRphysBase_MSR(1)
441 .long MTRRphysMask_MSR(1)
442 .long MTRRphysBase_MSR(2)
443 .long MTRRphysMask_MSR(2)
444 .long MTRRphysBase_MSR(3)
445 .long MTRRphysMask_MSR(3)
446 .long MTRRphysBase_MSR(4)
447 .long MTRRphysMask_MSR(4)
448 .long MTRRphysBase_MSR(5)
449 .long MTRRphysMask_MSR(5)
450 .long MTRRphysBase_MSR(6)
451 .long MTRRphysMask_MSR(6)
452 .long MTRRphysBase_MSR(7)
453 .long MTRRphysMask_MSR(7)
Uwe Hermann42926842010-09-30 23:15:36 +0000454
Warren Turkal4ffde942010-10-12 06:13:40 +0000455 /* Variable IORR MTRR MSRs */
456 .long IORRBase_MSR(0)
457 .long IORRMask_MSR(0)
458 .long IORRBase_MSR(1)
459 .long IORRMask_MSR(1)
Uwe Hermann42926842010-09-30 23:15:36 +0000460
Warren Turkal4ffde942010-10-12 06:13:40 +0000461 /* Top of memory MTRR MSRs */
462 .long TOP_MEM_MSR
463 .long TOP_MEM2_MSR
464
Marc Jones2006b382007-12-19 00:47:09 +0000465 .long 0x000 /* NULL, end of table */
466
Stefan Reinauer806e1462005-12-01 10:54:44 +0000467cache_as_ram_setup_out: