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Uwe Hermann06694a82010-09-23 18:16:46 +00001/*
2 * This file is part of the coreboot project.
3 *
Uwe Hermann06694a82010-09-23 18:16:46 +00004 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
Uwe Hermann06694a82010-09-23 18:16:46 +000013 */
14
Martin Rotheffaf8f2019-10-20 20:29:22 -060015 /* This came from the Linux kernel (include/linux/usb/ehci_def.h). */
16
Yinghai Lud57241f2007-02-28 11:17:02 +000017#ifndef EHCI_H
18#define EHCI_H
19
Uwe Hermann06694a82010-09-23 18:16:46 +000020/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
Yinghai Lud57241f2007-02-28 11:17:02 +000021
Uwe Hermann06694a82010-09-23 18:16:46 +000022/* Section 2.2 Host Controller Capability Registers */
23struct ehci_caps {
24 /* these fields are specified as 8 and 16 bit registers,
25 * but some hosts can't perform 8 or 16 bit PCI accesses.
26 */
27 u32 hc_capbase;
28#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
29#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
30 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
31#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
32#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
33#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
34#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
35#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
36#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
37#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
38
39 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
40/* EHCI 1.1 addendum */
41#define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19))
42#define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18))
43#define HCC_LPM(p) ((p)&(1 << 17))
44#define HCC_HW_PREFETCH(p) ((p)&(1 << 16))
45
46#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
Yinghai Lud57241f2007-02-28 11:17:02 +000047#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
48#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
Uwe Hermann06694a82010-09-23 18:16:46 +000049#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
Yinghai Lud57241f2007-02-28 11:17:02 +000050#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
51#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
Uwe Hermann06694a82010-09-23 18:16:46 +000052 u8 portroute[8]; /* nibbles for routing - offset 0xC */
Stefan Reinauer6a001132017-07-13 02:20:27 +020053} __packed;
Yinghai Lud57241f2007-02-28 11:17:02 +000054
Uwe Hermann06694a82010-09-23 18:16:46 +000055
Yinghai Lud57241f2007-02-28 11:17:02 +000056/* Section 2.3 Host Controller Operational Registers */
57struct ehci_regs {
58
Uwe Hermann06694a82010-09-23 18:16:46 +000059 /* USBCMD: offset 0x00 */
60 u32 command;
61
62/* EHCI 1.1 addendum */
63#define CMD_HIRD (0xf<<24) /* host initiated resume duration */
64#define CMD_PPCEE (1<<15) /* per port change event enable */
65#define CMD_FSP (1<<14) /* fully synchronized prefetch */
66#define CMD_ASPE (1<<13) /* async schedule prefetch enable */
67#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */
Yinghai Lud57241f2007-02-28 11:17:02 +000068/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
Uwe Hermann06694a82010-09-23 18:16:46 +000069#define CMD_PARK (1<<11) /* enable "park" on async qh */
70#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
71#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
72#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
73#define CMD_ASE (1<<5) /* async schedule enable */
74#define CMD_PSE (1<<4) /* periodic schedule enable */
Yinghai Lud57241f2007-02-28 11:17:02 +000075/* 3:2 is periodic frame list size */
Uwe Hermann06694a82010-09-23 18:16:46 +000076#define CMD_RESET (1<<1) /* reset HC not bus */
77#define CMD_RUN (1<<0) /* start/stop HC */
Yinghai Lud57241f2007-02-28 11:17:02 +000078
Uwe Hermann06694a82010-09-23 18:16:46 +000079 /* USBSTS: offset 0x04 */
80 u32 status;
81#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */
82#define STS_ASS (1<<15) /* Async Schedule Status */
83#define STS_PSS (1<<14) /* Periodic Schedule Status */
84#define STS_RECL (1<<13) /* Reclamation */
85#define STS_HALT (1<<12) /* Not running (any reason) */
Yinghai Lud57241f2007-02-28 11:17:02 +000086/* some bits reserved */
Uwe Hermann06694a82010-09-23 18:16:46 +000087 /* these STS_* flags are also intr_enable bits (USBINTR) */
88#define STS_IAA (1<<5) /* Interrupted on async advance */
89#define STS_FATAL (1<<4) /* such as some PCI access errors */
90#define STS_FLR (1<<3) /* frame list rolled over */
91#define STS_PCD (1<<2) /* port change detect */
92#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
93#define STS_INT (1<<0) /* "normal" completion (short, ...) */
Yinghai Lud57241f2007-02-28 11:17:02 +000094
Uwe Hermann06694a82010-09-23 18:16:46 +000095 /* USBINTR: offset 0x08 */
96 u32 intr_enable;
Yinghai Lud57241f2007-02-28 11:17:02 +000097
Uwe Hermann06694a82010-09-23 18:16:46 +000098 /* FRINDEX: offset 0x0C */
99 u32 frame_index; /* current microframe number */
100 /* CTRLDSSEGMENT: offset 0x10 */
101 u32 segment; /* address bits 63:32 if needed */
102 /* PERIODICLISTBASE: offset 0x14 */
103 u32 frame_list; /* points to periodic list */
104 /* ASYNCLISTADDR: offset 0x18 */
105 u32 async_next; /* address of next async queue head */
Yinghai Lud57241f2007-02-28 11:17:02 +0000106
Uwe Hermann06694a82010-09-23 18:16:46 +0000107 u32 reserved[9];
Yinghai Lud57241f2007-02-28 11:17:02 +0000108
Uwe Hermann06694a82010-09-23 18:16:46 +0000109 /* CONFIGFLAG: offset 0x40 */
110 u32 configured_flag;
111#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
Yinghai Lud57241f2007-02-28 11:17:02 +0000112
Uwe Hermann06694a82010-09-23 18:16:46 +0000113 /* PORTSC: offset 0x44 */
114 u32 port_status[0]; /* up to N_PORTS */
115/* EHCI 1.1 addendum */
116#define PORTSC_SUSPEND_STS_ACK 0
117#define PORTSC_SUSPEND_STS_NYET 1
118#define PORTSC_SUSPEND_STS_STALL 2
119#define PORTSC_SUSPEND_STS_ERR 3
120
121#define PORT_DEV_ADDR (0x7f<<25) /* device address */
122#define PORT_SSTS (0x3<<23) /* suspend status */
Yinghai Lud57241f2007-02-28 11:17:02 +0000123/* 31:23 reserved */
Uwe Hermann06694a82010-09-23 18:16:46 +0000124#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
125#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
126#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
Yinghai Lud57241f2007-02-28 11:17:02 +0000127/* 19:16 for port testing */
Uwe Hermann06694a82010-09-23 18:16:46 +0000128#define PORT_TEST_PKT (0x4<<16) /* Port Test Control - packet test */
129#define PORT_LED_OFF (0<<14)
130#define PORT_LED_AMBER (1<<14)
131#define PORT_LED_GREEN (2<<14)
132#define PORT_LED_MASK (3<<14)
133#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
134#define PORT_POWER (1<<12) /* true: has power (see PPC) */
135#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
Yinghai Lud57241f2007-02-28 11:17:02 +0000136/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
137/* 9 reserved */
Uwe Hermann06694a82010-09-23 18:16:46 +0000138#define PORT_LPM (1<<9) /* LPM transaction */
139#define PORT_RESET (1<<8) /* reset port */
140#define PORT_SUSPEND (1<<7) /* suspend port */
141#define PORT_RESUME (1<<6) /* resume it */
142#define PORT_OCC (1<<5) /* over current change */
143#define PORT_OC (1<<4) /* over current active */
144#define PORT_PEC (1<<3) /* port enable change */
145#define PORT_PE (1<<2) /* port enable */
146#define PORT_CSC (1<<1) /* connect status change */
147#define PORT_CONNECT (1<<0) /* device connected */
Yinghai Lud57241f2007-02-28 11:17:02 +0000148#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
Stefan Reinauer6a001132017-07-13 02:20:27 +0200149} __packed;
Yinghai Lud57241f2007-02-28 11:17:02 +0000150
Uwe Hermann06694a82010-09-23 18:16:46 +0000151#define USBMODE 0x68 /* USB Device mode */
152#define USBMODE_SDIS (1<<3) /* Stream disable */
153#define USBMODE_BE (1<<2) /* BE/LE endianness select */
154#define USBMODE_CM_HC (3<<0) /* host controller mode */
155#define USBMODE_CM_IDLE (0<<0) /* idle state */
156
157/* Moorestown has some non-standard registers, partially due to the fact that
Martin Roth0cb07e32013-07-09 21:46:01 -0600158 * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
Uwe Hermann06694a82010-09-23 18:16:46 +0000159 * PORTSCx
160 */
161#define HOSTPC0 0x84 /* HOSTPC extension */
162#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
163#define HOSTPC_PSPD (3<<25) /* Port speed detection */
164#define USBMODE_EX 0xc8 /* USB Device mode extension */
165#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
166#define USBMODE_EX_HC (3<<0) /* host controller mode */
167#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */
168#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
169
Yinghai Lud57241f2007-02-28 11:17:02 +0000170/* Appendix C, Debug port ... intended for use with special "debug devices"
171 * that can help if there's no serial console. (nonstandard enumeration.)
172 */
173struct ehci_dbg_port {
Uwe Hermann06694a82010-09-23 18:16:46 +0000174 u32 control;
175#define DBGP_OWNER (1<<30)
176#define DBGP_ENABLED (1<<28)
177#define DBGP_DONE (1<<16)
178#define DBGP_INUSE (1<<10)
179#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
180# define DBGP_ERR_BAD 1
181# define DBGP_ERR_SIGNAL 2
182#define DBGP_ERROR (1<<6)
183#define DBGP_GO (1<<5)
184#define DBGP_OUT (1<<4)
185#define DBGP_LEN(x) (((x)>>0)&0x0f)
186 u32 pids;
187#define DBGP_PID_GET(x) (((x)>>16)&0xff)
188#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
189 u32 data03;
190 u32 data47;
191 u32 address;
192#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
Stefan Reinauer6a001132017-07-13 02:20:27 +0200193} __packed;
Kyösti Mälkki83fe6d72014-02-25 20:11:52 +0200194
195#define USB_DEBUG_DEVNUM 127
196
Sven Schnelle20fc6312011-10-30 09:57:35 +0100197#endif