Jakub Czapiga | d95d264 | 2023-05-30 08:57:17 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
Jakub Czapiga | 4bd1012 | 2023-05-30 09:48:09 +0000 | [diff] [blame] | 3 | /* This header block is used to supply information to arbitrage, a |
| 4 | * google-internal tool. Updating it incorrectly will lead to issues, |
| 5 | * so please don't update it unless a change is specifically required. |
| 6 | * BaseID: 3EC4CE58201758F4 |
| 7 | * Overrides: c826ba419f06f9df9cded8e60633253ddc7b60ff |
| 8 | */ |
| 9 | |
Jakub Czapiga | d95d264 | 2023-05-30 08:57:17 +0000 | [diff] [blame] | 10 | #include <baseboard/gpio.h> |
| 11 | #include <baseboard/variants.h> |
Jakub Czapiga | d95d264 | 2023-05-30 08:57:17 +0000 | [diff] [blame] | 12 | #include <soc/gpio.h> |
Jakub Czapiga | 4bd1012 | 2023-05-30 09:48:09 +0000 | [diff] [blame] | 13 | #include <console/console.h> |
| 14 | #include <boardid.h> |
| 15 | |
| 16 | /* Pad configuration in ramstage */ |
| 17 | static const struct pad_config gpio_table[] = { |
| 18 | /* GPP_A00 : [] ==> ESPI_SOC_IO0_R */ |
| 19 | PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE), |
| 20 | /* GPP_A01 : [] ==> ESPI_SOC_IO1_R */ |
| 21 | PAD_CFG_NF_IOSSTATE(GPP_A01, UP_20K, DEEP, NF1, IGNORE), |
| 22 | /* GPP_A02 : [] ==> ESPI_SOC_IO2_R */ |
| 23 | PAD_CFG_NF_IOSSTATE(GPP_A02, UP_20K, DEEP, NF1, IGNORE), |
| 24 | /* GPP_A03 : [] ==> ESPI_SOC_IO3_R */ |
| 25 | PAD_CFG_NF_IOSSTATE(GPP_A03, UP_20K, DEEP, NF1, IGNORE), |
| 26 | /* GPP_A04 : [] ==> ESPI_SOC_CS0_L */ |
| 27 | PAD_CFG_NF_IOSSTATE(GPP_A04, UP_20K, DEEP, NF1, IGNORE), |
| 28 | /* GPP_A05 : [] ==> ESPI_SOC_CLK_R */ |
| 29 | PAD_CFG_NF_IOSSTATE(GPP_A05, UP_20K, DEEP, NF1, IGNORE), |
| 30 | /* GPP_A06 : [] ==> ESPI_SOC_RESET_L */ |
| 31 | PAD_CFG_NF_IOSSTATE(GPP_A06, UP_20K, DEEP, NF1, IGNORE), |
| 32 | /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */ |
| 33 | PAD_NC(GPP_A11, NONE), |
| 34 | /* GPP_A12 : [] ==> EN_UCAM_PWR */ |
| 35 | PAD_NC(GPP_A12, NONE), |
| 36 | /* GPP_A13 : [] ==> SD_PE_PRSNT_L */ |
| 37 | PAD_CFG_GPI_LOCK(GPP_A13, NONE, LOCK_CONFIG), |
| 38 | /* GPP_A14 : [] ==> WWAN_RF_DISABLE_ODL */ |
| 39 | PAD_NC(GPP_A14, NONE), |
| 40 | /* GPP_A15 : [] ==> WWAN_RST_L */ |
| 41 | PAD_NC(GPP_A15, NONE), |
| 42 | /* GPP_A16 : [] ==> ESPI_SOC_ALERT_L */ |
| 43 | PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE), |
| 44 | /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ |
| 45 | PAD_CFG_GPI_IRQ_WAKE(GPP_A17, NONE, PLTRST, LEVEL, INVERT), |
| 46 | /* GPP_A18 : [] ==> CAM_PSW_L */ |
| 47 | PAD_NC(GPP_A18, NONE), |
| 48 | /* GPP_A19 : [] ==> EN_PP3300_SSD */ |
| 49 | PAD_CFG_GPO(GPP_A19, 1, DEEP), |
| 50 | /* GPP_A20 : [] ==> SSD_PERST_L */ |
| 51 | PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG), |
| 52 | /* GPP_A21 : [] ==> WWAN_CONFIG2 */ |
| 53 | PAD_NC(GPP_A21, NONE), |
| 54 | |
| 55 | /* GPP_B00 : [] ==> TCHPAD_INT_ODL */ |
| 56 | PAD_NC(GPP_B00, NONE), |
| 57 | /* GPP_B01 : [] ==> BT_DISABLE_L */ |
| 58 | PAD_CFG_GPO(GPP_B01, 1, DEEP), |
| 59 | /* GPP_B02 : [] ==> SOC_ISH_I2C_SENSOR_SDA */ |
| 60 | PAD_CFG_NF_LOCK(GPP_B02, NONE, NF3, LOCK_CONFIG), |
| 61 | /* GPP_B03 : [] ==> SOC_ISH_I2C_SENSOR_SCL */ |
| 62 | PAD_CFG_NF_LOCK(GPP_B03, NONE, NF3, LOCK_CONFIG), |
| 63 | /* GPP_B04 : [] ==> GPP_B04_STRAP */ |
| 64 | PAD_NC(GPP_B04, NONE), |
| 65 | /* GPP_B05 : [] ==> SPKR_INT_L_R */ |
| 66 | PAD_CFG_GPI(GPP_B05, NONE, DEEP), |
| 67 | /* GPP_B06 : [] ==> HP_INT_L_R */ |
| 68 | PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH), |
| 69 | /* GPP_B07 : [] ==> RST_HP_L */ |
| 70 | PAD_CFG_GPO(GPP_B07, 1, DEEP), |
| 71 | /* GPP_B08 : [] ==> PWM_BUZZER */ |
| 72 | PAD_CFG_NF(GPP_B08, NONE, DEEP, NF2), |
| 73 | /* GPP_B09 : [] ==> GPP_B09 */ |
| 74 | PAD_NC(GPP_B09, NONE), |
| 75 | /* GPP_B10 : [] ==> WIFI_DISABLE_L */ |
| 76 | PAD_CFG_GPO(GPP_B10, 1, DEEP), |
| 77 | /* GPP_B11 : [] ==> EN_FP_PWR */ |
| 78 | PAD_NC(GPP_B11, NONE), |
| 79 | /* GPP_B12 : [] ==> SLP_S0_R_L */ |
| 80 | PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), |
| 81 | /* GPP_B13 : [] ==> PLT_RST_L */ |
| 82 | PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), |
| 83 | /* GPP_B14 : [] ==> GPP_B14_STRAP */ |
| 84 | PAD_NC(GPP_B14, NONE), |
| 85 | /* GPP_B15 : [] ==> USB_A_OC_ODL */ |
| 86 | PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), |
| 87 | /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ |
| 88 | PAD_NC(GPP_B16, NONE), |
| 89 | /* GPP_B17 : [] ==> EN_WWAN_RAILS */ |
| 90 | PAD_NC(GPP_B17, NONE), |
| 91 | /* GPP_B18 : [] ==> I2C4_SDA */ |
| 92 | PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), |
| 93 | /* GPP_B19 : [] ==> I2C4_SCL */ |
| 94 | PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), |
| 95 | /* GPP_B20 : [] ==> SOC_I2C_MISC_SDA */ |
| 96 | PAD_CFG_NF_LOCK(GPP_B20, NONE, NF2, LOCK_CONFIG), |
| 97 | /* GPP_B21 : [] ==> SOC_I2C_MISC_SCL */ |
| 98 | PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG), |
| 99 | /* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */ |
| 100 | PAD_CFG_GPO(GPP_B22, 0, DEEP), |
| 101 | /* GPP_B23 : [] ==> WWAN_CONFIG */ |
| 102 | PAD_NC(GPP_B23, NONE), |
| 103 | |
| 104 | /* GPP_C00 : [] ==> EN_TCHSCR_RAILS */ |
| 105 | PAD_NC(GPP_C00, NONE), |
| 106 | /* GPP_C01 : [] ==> SOC_TCHSCR_RST_ODL */ |
| 107 | PAD_NC(GPP_C01, NONE), |
| 108 | /* GPP_C02 : [] ==> SOC_TCHSCR_SPI_INT_STRAP */ |
| 109 | PAD_NC(GPP_C02, NONE), |
| 110 | /* GPP_C03 : [] ==> EN_WCAM_SENR_PWR */ |
| 111 | PAD_NC(GPP_C03, NONE), |
| 112 | /* GPP_C04 : [] ==> EN_WCAM_PWR */ |
| 113 | PAD_NC(GPP_C04, NONE), |
| 114 | /* GPP_C05 : [] ==> WWAN_PERST_L */ |
| 115 | PAD_NC(GPP_C05, NONE), |
| 116 | /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */ |
| 117 | PAD_NC(GPP_C06, NONE), |
| 118 | /* GPP_C07 : [] ==> SOC_TCHSCR_INT_L */ |
| 119 | PAD_NC(GPP_C07, NONE), |
| 120 | /* GPP_C08 : [] ==> SOCHOT_ODL */ |
| 121 | PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), |
| 122 | /* GPP_C09 : [] ==> MISC_SYNC_IN */ |
| 123 | PAD_NC(GPP_C09, NONE), |
Subrata Banik | 67c48a6 | 2023-06-30 21:59:11 -0700 | [diff] [blame^] | 124 | /* GPP_C10 : [] ==> EN_LAN_RAILS */ |
| 125 | PAD_CFG_GPO(GPP_C10, 1, DEEP), |
Jakub Czapiga | 4bd1012 | 2023-05-30 09:48:09 +0000 | [diff] [blame] | 126 | /* GPP_C11 : [] ==> SD_CLKREQ_ODL */ |
| 127 | PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), |
| 128 | /* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */ |
| 129 | PAD_NC(GPP_C12, NONE), |
| 130 | /* GPP_C13 : [] ==> LAN_PERST_L */ |
| 131 | PAD_CFG_GPO_LOCK(GPP_C13, 1, LOCK_CONFIG), |
| 132 | /* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */ |
| 133 | PAD_NC(GPP_C15, NONE), |
| 134 | /* GPP_C16 : [] ==> USB_C0_LSX_TX */ |
| 135 | PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), |
| 136 | /* GPP_C17 : [] ==> USB_C0_LSX_RX */ |
| 137 | PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), |
| 138 | /* GPP_C18 : [] ==> USB_C1_LSX_TX */ |
| 139 | PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), |
| 140 | /* GPP_C19 : [] ==> USB_C1_LSX_RX */ |
| 141 | PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), |
| 142 | /* GPP_C20 : [] ==> USB_C2_LSX_TX */ |
| 143 | PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), |
| 144 | /* GPP_C21 : [] ==> USB_C2_LSX_RX */ |
| 145 | PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), |
| 146 | /* GPP_C22 : [] ==> SOC_FPMCU_BOOT0 */ |
| 147 | PAD_NC(GPP_C22, NONE), |
| 148 | /* GPP_C23 : [] ==> SOC_FPMCU_RST_ODL */ |
| 149 | PAD_NC(GPP_C23, NONE), |
| 150 | |
| 151 | /* GPP_D00 : [] ==> WCAM_MCLK_R */ |
| 152 | PAD_NC(GPP_D00, NONE), |
| 153 | /* GPP_D01 : [] ==> SD_PE_WAKE_ODL */ |
| 154 | PAD_CFG_GPI_LOCK(GPP_D01, NONE, LOCK_CONFIG), |
| 155 | /* GPP_D02 : [] ==> SD_PERST_L */ |
| 156 | PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), |
| 157 | /* GPP_D03 : [] ==> EN_SD_RAILS */ |
| 158 | PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG), |
| 159 | /* GPP_D04 : [] ==> EN_SPKR */ |
| 160 | PAD_CFG_GPO(GPP_D04, 1, DEEP), |
| 161 | /* GPP_D05 : [] ==> SPARE_GPP_D05 */ |
| 162 | PAD_NC(GPP_D05, NONE), |
| 163 | /* GPP_D06 : [] ==> SPARE_GPP_D06 */ |
| 164 | PAD_NC(GPP_D06, NONE), |
| 165 | /* GPP_D07 : [] ==> FPMCU_UWB_MUX_SEL */ |
| 166 | PAD_NC(GPP_D07, NONE), |
| 167 | /* GPP_D08 : [] ==> SPARE_GPP_D08 */ |
| 168 | PAD_NC(GPP_D08, NONE), |
| 169 | /* GPP_D09 : [] ==> I2S_MCLK_R */ |
| 170 | PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), |
| 171 | /* GPP_D10 : [] ==> I2S_SPKR_SCLK_R */ |
| 172 | PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), |
| 173 | /* GPP_D11 : [] ==> I2S_SPKR_SFRM_R */ |
| 174 | PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), |
| 175 | /* GPP_D12 : [] ==> I2S_SOC_TX_SPKR_RX_R_STRAP */ |
| 176 | PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF2), |
| 177 | /* GPP_D13 : [] ==> I2S_SOC_RX_SPKR_TX */ |
| 178 | PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), |
| 179 | /* GPP_D14 : [] ==> I2S_HP_SCLK_R */ |
| 180 | PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), |
| 181 | /* GPP_D15 : [] ==> I2S_HP_SFRM_R */ |
| 182 | PAD_CFG_NF(GPP_D15, NONE, DEEP, NF2), |
| 183 | /* GPP_D16 : [] ==> I2S_SOC_TX_HP_RX_R */ |
| 184 | PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), |
| 185 | /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */ |
| 186 | PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), |
| 187 | /* GPP_D18 : [] ==> LAN_PE_WAKE_ODL */ |
| 188 | PAD_CFG_GPI_APIC_LOCK(GPP_D18, NONE, LEVEL, INVERT, LOCK_CONFIG), |
| 189 | /* GPP_D19 : [] ==> SSD_CLKREQ_ODL */ |
| 190 | PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), |
| 191 | /* GPP_D20 : [] ==> EN_LAN_RAILS */ |
| 192 | PAD_NC(GPP_D20, NONE), |
| 193 | /* GPP_D21 : [] ==> WLAN_CLKREQ_ODL */ |
| 194 | PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), |
| 195 | /* GPP_D22 : [] ==> NC */ |
| 196 | PAD_NC(GPP_D22, NONE), |
| 197 | /* GPP_D23 : [] ==> NC */ |
| 198 | PAD_NC(GPP_D23, NONE), |
| 199 | |
| 200 | /* GPP_E00 : [] ==> SAR_INT_L */ |
| 201 | PAD_NC(GPP_E00, NONE), |
| 202 | /* GPP_E01 : [] ==> MEM_STRAP_2 */ |
| 203 | PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), |
| 204 | /* GPP_E02 : [] ==> MEM_STRAP_1 */ |
| 205 | PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG), |
| 206 | /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ |
| 207 | PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), |
| 208 | /* GPP_E04 : [] ==> HPS_INT_L */ |
| 209 | PAD_NC(GPP_E04, NONE), |
| 210 | /* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */ |
| 211 | PAD_CFG_GPO(GPP_E05, 1, DEEP), |
| 212 | /* GPP_E06 : [] ==> GPP_E06_STRAP */ |
| 213 | PAD_NC(GPP_E06, NONE), |
| 214 | /* GPP_E07 : [] ==> WWAN_FCPO_L */ |
| 215 | PAD_NC(GPP_E07, NONE), |
| 216 | /* GPP_E08 : [] ==> SAR2_INT_L */ |
| 217 | PAD_NC(GPP_E08, NONE), |
| 218 | /* GPP_E09 : [] ==> USB_C_OC_ODL */ |
| 219 | PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), |
| 220 | /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */ |
| 221 | PAD_NC(GPP_E10, NONE), |
| 222 | /* GPP_E11 : [] ==> MEM_STRAP_0 */ |
| 223 | PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), |
| 224 | /* GPP_E12 : [] ==> MEM_STRAP_3 */ |
| 225 | PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), |
| 226 | /* GPP_E13 : [] ==> MEM_CH_SEL */ |
| 227 | PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), |
| 228 | /* GPP_E14 : [] ==> SOC_EDP_HPD_L */ |
| 229 | PAD_NC(GPP_E14, NONE), |
| 230 | /* GPP_E15 : [] ==> NC */ |
| 231 | PAD_NC(GPP_E15, NONE), |
| 232 | /* GPP_E16 : [] ==> GPP_E16 */ |
| 233 | PAD_NC(GPP_E16, NONE), |
| 234 | /* GPP_E17 : [] ==> EN_HPS_PWR */ |
| 235 | PAD_NC(GPP_E17, NONE), |
| 236 | /* GPP_E22 : [] ==> EN_WLAN_RAILS */ |
| 237 | PAD_CFG_GPO(GPP_E22, 1, DEEP), |
| 238 | |
| 239 | /* GPP_F00 : [] ==> CNV_BRI_DT_R */ |
| 240 | PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), |
| 241 | /* GPP_F01 : [] ==> CNV_BRI_RSP */ |
| 242 | PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), |
| 243 | /* GPP_F02 : [] ==> CNV_RGI_DT_R */ |
| 244 | PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), |
| 245 | /* GPP_F03 : [] ==> CNV_RGI_RSP */ |
| 246 | PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), |
| 247 | /* GPP_F04 : [] ==> CNV_RF_RST_L */ |
| 248 | PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), |
| 249 | /* GPP_F05 : [] ==> WLAN_CNVI_CLKREQ_ODL */ |
| 250 | PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), |
| 251 | /* GPP_F06 : [] ==> WWAN_WLAN_COEX3 */ |
| 252 | PAD_NC(GPP_F06, NONE), |
| 253 | /* GPP_F07 : [] ==> UCAM_MCLK_R */ |
| 254 | PAD_NC(GPP_F07, NONE), |
| 255 | /* GPP_F08 : [] ==> WLAN_PERST_L */ |
| 256 | PAD_CFG_GPO(GPP_F08, 1, DEEP), |
| 257 | /* GPP_F09 : [] ==> WLAN_PE_WAKE_ODL */ |
| 258 | PAD_CFG_GPI_IRQ_WAKE(GPP_F09, NONE, PLTRST, LEVEL, INVERT), |
| 259 | /* GPP_F10 : [] ==> WWAN_PE_WAKE_ODL */ |
| 260 | PAD_NC(GPP_F10, NONE), |
| 261 | /* GPP_F11 : [] ==> GSP1_SOC_CLK_R */ |
| 262 | PAD_NC(GPP_F11, NONE), |
| 263 | /* GPP_F12 : [] ==> Net Name Correction: GSPI1_SOC_DO_FPMCU_DI_R */ |
| 264 | PAD_NC(GPP_F12, NONE), |
| 265 | /* GPP_F13 : [] ==> Net Name Correction: GSPI1_SOC_DI_FPMCU_DO_LS */ |
| 266 | PAD_NC(GPP_F13, NONE), |
| 267 | /* GPP_F14 : [] ==> GSPI_SOC_DO_TCHSCR_DI */ |
| 268 | PAD_NC(GPP_F14, NONE), |
| 269 | /* GPP_F15 : [] ==> GSPI_SOC_DI_TCHSCR_DO */ |
| 270 | PAD_NC(GPP_F15, NONE), |
| 271 | /* GPP_F16 : [] ==> GSPI_SOC_TCHSCR_CLK */ |
| 272 | PAD_NC(GPP_F16, NONE), |
| 273 | /* GPP_F17 : [] ==> GSPI1_SOC_CS_L */ |
| 274 | PAD_NC(GPP_F17, NONE), |
| 275 | /* GPP_F18 : [] ==> GSPI_SOC_TCHSCR_CS_L */ |
| 276 | PAD_NC(GPP_F18, NONE), |
| 277 | /* GPP_F19 : [] ==> GPP_F19_STRAP */ |
| 278 | PAD_NC(GPP_F19, NONE), |
| 279 | /* GPP_F20 : [] ==> GPP_F20_STRAP */ |
| 280 | PAD_NC(GPP_F20, NONE), |
| 281 | /* GPP_F21 : [] ==> GPP_F21_STRAP */ |
| 282 | PAD_NC(GPP_F21, NONE), |
| 283 | /* GPP_F22 : [] ==> NC */ |
| 284 | PAD_NC(GPP_F22, NONE), |
| 285 | /* GPP_F23 : [] ==> NC */ |
| 286 | PAD_NC(GPP_F23, NONE), |
| 287 | |
| 288 | /* GPP_H00 : [] ==> GPP_H00_STRAP */ |
| 289 | PAD_NC(GPP_H00, NONE), |
| 290 | /* GPP_H01 : [] ==> GPP_H01_STRAP */ |
| 291 | PAD_NC(GPP_H01, NONE), |
| 292 | /* GPP_H02 : [] ==> GPP_H02_STRAP */ |
| 293 | PAD_NC(GPP_H02, NONE), |
| 294 | /* GPP_H04 : [] ==> WWAN_WLAN_COEX1 */ |
| 295 | PAD_NC(GPP_H04, NONE), |
| 296 | /* GPP_H05 : [] ==> WWAN_WLAN_COEX2 */ |
| 297 | PAD_NC(GPP_H05, NONE), |
| 298 | /* GPP_H06 : [] ==> SOC_I2C_TCHPAD_SDA */ |
| 299 | PAD_CFG_NF_LOCK(GPP_H06, NONE, NF1, LOCK_CONFIG), |
| 300 | /* GPP_H07 : [] ==> SOC_I2C_TCHPAD_SCL */ |
| 301 | PAD_CFG_NF_LOCK(GPP_H07, NONE, NF1, LOCK_CONFIG), |
| 302 | /* GPP_H08 : [] ==> UART_SOC_RX_DEBUG_TX */ |
| 303 | PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), |
| 304 | /* GPP_H09 : [] ==> UART_SOC_TX_DEBUG_RX */ |
| 305 | PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), |
| 306 | /* GPP_H10 : [] ==> SOC_WP_OD */ |
| 307 | PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), |
| 308 | /* GPP_H11 : [] ==> USB_A1_RT_RST_ODL */ |
| 309 | PAD_NC(GPP_H11, NONE), |
| 310 | /* GPP_H13 : [] ==> CPU_C10_GATE_L */ |
| 311 | PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), |
| 312 | /* GPP_H14 : [] ==> SLP_S0_GATE_R */ |
| 313 | PAD_CFG_GPO(GPP_H14, 1, PLTRST), |
| 314 | /* GPP_H15 : [] ==> EN_DMIC_SOC_DATA */ |
| 315 | PAD_CFG_GPO(GPP_H15, 0, PLTRST), |
| 316 | /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK */ |
| 317 | PAD_NC(GPP_H16, NONE), |
| 318 | /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */ |
| 319 | PAD_NC(GPP_H17, NONE), |
| 320 | /* GPP_H19 : [] ==> SOC_I2C_AUD_WFC_SDA */ |
| 321 | PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), |
| 322 | /* GPP_H20 : [] ==> SOC_I2C_AUD_WFC_SCL */ |
| 323 | PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), |
| 324 | /* GPP_H21 : [] ==> SOC_I2C_TCHSCR_SDA */ |
| 325 | PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), |
| 326 | /* GPP_H22 : [] ==> SOC_I2C_TCHSCR_SCL */ |
| 327 | PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), |
| 328 | |
| 329 | /* GPP_S00 : [] ==> SDW_HP_CLK */ |
| 330 | PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), |
| 331 | /* GPP_S01 : [] ==> SDW_HP_DATA */ |
| 332 | PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), |
| 333 | /* GPP_S02 : [] ==> DMIC_SOC_CLK0_DB_RC */ |
| 334 | PAD_NC(GPP_S02, NONE), |
| 335 | /* GPP_S03 : [] ==> DMIC_SOC_DATA0_DB_R */ |
| 336 | PAD_NC(GPP_S03, NONE), |
| 337 | /* GPP_S04 : [] ==> SDW_SPKR_CLK */ |
| 338 | PAD_CFG_NF(GPP_S04, NONE, DEEP, NF1), |
| 339 | /* GPP_S05 : [] ==> SDW_SPKR_DATA */ |
| 340 | PAD_CFG_NF(GPP_S05, NONE, DEEP, NF1), |
| 341 | /* GPP_S06 : [] ==> DMIC_SOC_CLK1_DB_RC */ |
| 342 | PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), |
| 343 | /* GPP_S07 : [] ==> DMIC_SOC_DATA1_DB */ |
| 344 | PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), |
| 345 | |
| 346 | /* GPP_V00 : [] ==> BATLOW_L */ |
| 347 | PAD_NC(GPP_V00, NONE), |
| 348 | /* GPP_V01 : [] ==> ACPRESENT */ |
| 349 | PAD_NC(GPP_V01, NONE), |
| 350 | /* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */ |
| 351 | PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), |
| 352 | /* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */ |
| 353 | PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), |
| 354 | /* GPP_V04 : [] ==> SLP_S3_L */ |
| 355 | PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), |
| 356 | /* GPP_V05 : [] ==> SLP_S4_L */ |
| 357 | PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), |
| 358 | /* GPP_V06 : [] ==> SLP_A_L */ |
| 359 | PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), |
| 360 | /* GPP_V08 : [] ==> SOC_SUSCLK */ |
| 361 | PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), |
| 362 | /* GPP_V09 : [] ==> SOC_SLP_WLAN_L */ |
| 363 | PAD_NC(GPP_V09, NONE), |
| 364 | /* GPP_V10 : [] ==> SLP_S5_L */ |
| 365 | PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), |
| 366 | /* GPP_V11 : [] ==> SOC_GPP_V11 */ |
| 367 | PAD_NC(GPP_V11, NONE), |
| 368 | /* GPP_V12 : [] ==> SOC_SLP_LAN_L */ |
| 369 | PAD_CFG_NF(GPP_F17, NONE, DEEP, NF8), |
| 370 | /* GPP_V14 : [] ==> SOC_WAKE_L */ |
| 371 | PAD_NC(GPP_V14, NONE), |
| 372 | /* GPP_V22 : [] ==> WCAM_RST_L */ |
| 373 | PAD_NC(GPP_V22, NONE), |
| 374 | /* GPP_V23 : [] ==> UCAM_RST_L */ |
| 375 | PAD_NC(GPP_V23, NONE), |
| 376 | }; |
| 377 | |
| 378 | /* Early pad configuration in bootblock */ |
| 379 | static const struct pad_config early_gpio_table[] = { |
| 380 | /* GPP_B18 : [] ==> I2C4_SDA */ |
| 381 | PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), |
| 382 | /* GPP_B19 : [] ==> I2C4_SCL */ |
| 383 | PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), |
| 384 | /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ |
| 385 | PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), |
| 386 | |
| 387 | /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ |
| 388 | PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), |
| 389 | /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ |
| 390 | PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), |
| 391 | |
| 392 | /* GPP_D03 : [] ==> EN_SD_RAILS */ |
| 393 | PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG), |
| 394 | |
| 395 | /* GPP_E13 : [] ==> MEM_CH_SEL */ |
| 396 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 397 | |
| 398 | /* GPP_A20 : [] ==> SSD_PERST_L */ |
| 399 | PAD_CFG_GPO(GPP_A20, 0, DEEP), |
| 400 | |
| 401 | /* GPP_H10 : [] ==> SOC_WP_OD */ |
| 402 | PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), |
| 403 | }; |
| 404 | |
| 405 | static const struct pad_config romstage_gpio_table[] = { |
| 406 | /* A20 : [] ==> SSD_PERST_L */ |
| 407 | PAD_CFG_GPO(GPP_A20, 0, DEEP), |
| 408 | /* GPP_D02 : [] ==> SD_PERST_L */ |
| 409 | PAD_CFG_GPO(GPP_D02, 1, DEEP), |
| 410 | }; |
Jakub Czapiga | d95d264 | 2023-05-30 08:57:17 +0000 | [diff] [blame] | 411 | |
| 412 | const struct pad_config *variant_gpio_table(size_t *num) |
| 413 | { |
Jakub Czapiga | 4bd1012 | 2023-05-30 09:48:09 +0000 | [diff] [blame] | 414 | *num = ARRAY_SIZE(gpio_table); |
| 415 | return gpio_table; |
Jakub Czapiga | d95d264 | 2023-05-30 08:57:17 +0000 | [diff] [blame] | 416 | } |
| 417 | |
| 418 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 419 | { |
Jakub Czapiga | 4bd1012 | 2023-05-30 09:48:09 +0000 | [diff] [blame] | 420 | *num = ARRAY_SIZE(early_gpio_table); |
| 421 | return early_gpio_table; |
| 422 | } |
| 423 | |
| 424 | /* Create the stub for romstage gpio, typically use for power sequence */ |
| 425 | const struct pad_config *variant_romstage_gpio_table(size_t *num) |
| 426 | { |
| 427 | *num = ARRAY_SIZE(romstage_gpio_table); |
| 428 | return romstage_gpio_table; |
Jakub Czapiga | d95d264 | 2023-05-30 08:57:17 +0000 | [diff] [blame] | 429 | } |
| 430 | |
| 431 | static const struct cros_gpio cros_gpios[] = { |
Jakub Czapiga | 4bd1012 | 2023-05-30 09:48:09 +0000 | [diff] [blame] | 432 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 433 | CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), |
Jakub Czapiga | d95d264 | 2023-05-30 08:57:17 +0000 | [diff] [blame] | 434 | }; |
| 435 | |
| 436 | DECLARE_CROS_GPIOS(cros_gpios); |