Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2015 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
Aaron Durbin | 39bdb0b | 2015-08-04 23:59:43 -0500 | [diff] [blame] | 21 | #include <arch/acpi.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 22 | #include <cbmem.h> |
| 23 | #include <cbfs.h> |
| 24 | #include <console/console.h> |
| 25 | #include <fsp_util.h> |
| 26 | #include <lib.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 27 | #include <soc/intel/common/memmap.h> |
| 28 | #include <soc/intel/common/ramstage.h> |
| 29 | #include <stage_cache.h> |
Aaron Durbin | 39bdb0b | 2015-08-04 23:59:43 -0500 | [diff] [blame] | 30 | #include <string.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 31 | #include <timestamp.h> |
| 32 | |
| 33 | /* SOC initialization after FSP silicon init */ |
| 34 | __attribute__((weak)) void soc_after_silicon_init(void) |
| 35 | { |
| 36 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 37 | } |
| 38 | |
| 39 | /* |
| 40 | * SMM Memory Map: |
| 41 | * |
| 42 | * +--------------------------+ smm_region_size() ----. |
| 43 | * | FSP Cache | CONFIG_FSP_CACHE_SIZE | |
| 44 | * +--------------------------+ | |
| 45 | * | SMM Ramstage Cache | + CONFIG_SMM_RESERVED_SIZE |
| 46 | * +--------------------------+ ---------------------' |
| 47 | * | SMM Code | |
| 48 | * +--------------------------+ smm_base |
| 49 | * |
| 50 | */ |
| 51 | |
| 52 | void stage_cache_external_region(void **base, size_t *size) |
| 53 | { |
| 54 | size_t cache_size; |
| 55 | u8 *cache_base; |
| 56 | |
| 57 | /* Determine the location of the ramstage cache */ |
| 58 | smm_region((void **)&cache_base, &cache_size); |
| 59 | *size = CONFIG_SMM_RESERVED_SIZE - CONFIG_FSP_CACHE_SIZE; |
| 60 | *base = &cache_base[cache_size - CONFIG_SMM_RESERVED_SIZE]; |
| 61 | } |
| 62 | |
| 63 | static void *smm_fsp_cache_base(size_t *size) |
| 64 | { |
| 65 | size_t cache_size; |
| 66 | u8 *cache_base; |
| 67 | |
| 68 | /* Determine the location of the FSP cache */ |
| 69 | stage_cache_external_region((void **)&cache_base, &cache_size); |
| 70 | *size = CONFIG_FSP_CACHE_SIZE; |
| 71 | return &cache_base[cache_size]; |
| 72 | } |
| 73 | |
| 74 | /* Display SMM memory map */ |
| 75 | static void smm_memory_map(void) |
| 76 | { |
| 77 | u8 *smm_base; |
| 78 | size_t smm_bytes; |
| 79 | size_t smm_code_bytes; |
| 80 | u8 *fsp_cache; |
| 81 | size_t fsp_cache_bytes; |
| 82 | u8 *ramstage_cache; |
| 83 | size_t ramstage_cache_bytes; |
| 84 | u8 *smm_reserved; |
| 85 | size_t smm_reserved_bytes; |
| 86 | |
| 87 | /* Locate the SMM regions */ |
| 88 | smm_region((void **)&smm_base, &smm_bytes); |
| 89 | fsp_cache = smm_fsp_cache_base(&fsp_cache_bytes); |
| 90 | stage_cache_external_region((void **)&ramstage_cache, &ramstage_cache_bytes); |
| 91 | smm_code_bytes = ramstage_cache - smm_base; |
| 92 | smm_reserved = fsp_cache + fsp_cache_bytes; |
| 93 | smm_reserved_bytes = smm_bytes - fsp_cache_bytes - ramstage_cache_bytes |
| 94 | - smm_code_bytes; |
| 95 | |
| 96 | /* Display the SMM regions */ |
| 97 | printk(BIOS_SPEW, "\nLocation SMM Memory Map Offset\n"); |
| 98 | if (smm_reserved_bytes) { |
| 99 | printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", |
| 100 | &smm_reserved[smm_reserved_bytes], (u32)smm_bytes); |
| 101 | printk(BIOS_SPEW, " | Other reserved region |\n"); |
| 102 | } |
| 103 | printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", |
| 104 | smm_reserved, (u32)(smm_reserved - smm_base)); |
| 105 | printk(BIOS_SPEW, " | FSP binary cache |\n"); |
| 106 | printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", |
| 107 | fsp_cache, (u32)(fsp_cache - smm_base)); |
| 108 | printk(BIOS_SPEW, " | ramstage cache |\n"); |
| 109 | printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", |
| 110 | ramstage_cache, (u32)(ramstage_cache - smm_base)); |
| 111 | printk(BIOS_SPEW, " | SMM code |\n"); |
| 112 | printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", |
| 113 | smm_base, 0); |
| 114 | printk(BIOS_ERR, "\nCONFIG_FSP_CACHE_SIZE: 0x%08x bytes\n\n", |
| 115 | CONFIG_FSP_CACHE_SIZE); |
| 116 | } |
| 117 | |
| 118 | struct smm_fsp_cache_header { |
| 119 | void *start; |
| 120 | size_t size; |
| 121 | FSP_INFO_HEADER *fih; |
| 122 | }; |
| 123 | |
| 124 | /* SoC implementation for caching support code. */ |
| 125 | static void soc_save_support_code(void *start, size_t size, |
| 126 | FSP_INFO_HEADER *fih) |
| 127 | { |
| 128 | u8 *fsp_cache; |
| 129 | size_t fsp_cache_length; |
| 130 | struct smm_fsp_cache_header *header; |
| 131 | size_t smm_fsp_cache_length; |
| 132 | |
| 133 | if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP)) |
| 134 | smm_memory_map(); |
| 135 | |
| 136 | /* Locate the FSP cache in SMM */ |
| 137 | fsp_cache = smm_fsp_cache_base(&smm_fsp_cache_length); |
| 138 | |
| 139 | /* Initialize the FSP cache header */ |
| 140 | header = (struct smm_fsp_cache_header *)fsp_cache; |
| 141 | fsp_cache += sizeof(*header); |
| 142 | header->start = start; |
| 143 | header->size = size; |
| 144 | header->fih = fih; |
| 145 | |
| 146 | /* Validate the CONFIG_FSP_CACHE_SIZE value */ |
| 147 | fsp_cache_length = sizeof(*header) + size; |
| 148 | if (smm_fsp_cache_length < fsp_cache_length) { |
| 149 | printk(BIOS_ERR, "CONFIG_FSP_CACHE_SIZE < 0x%08x bytes\n", |
| 150 | (u32)fsp_cache_length); |
| 151 | die("ERROR: Insufficent space to cache FSP binary!\n"); |
| 152 | } |
| 153 | |
| 154 | /* Copy the FSP binary into the SMM region for safe keeping */ |
| 155 | memcpy(fsp_cache, start, size); |
| 156 | } |
| 157 | |
| 158 | /* SoC implementation for restoring support code after S3 resume. Returns |
| 159 | * previously passed fih pointer from soc_save_support_code(). */ |
| 160 | static FSP_INFO_HEADER *soc_restore_support_code(void) |
| 161 | { |
| 162 | u8 *fsp_cache; |
| 163 | struct smm_fsp_cache_header *header; |
| 164 | size_t smm_fsp_cache_length; |
| 165 | |
| 166 | /* Locate the FSP cache in SMM */ |
| 167 | fsp_cache = smm_fsp_cache_base(&smm_fsp_cache_length); |
| 168 | |
| 169 | /* Get the FSP cache header */ |
| 170 | header = (struct smm_fsp_cache_header *)fsp_cache; |
| 171 | fsp_cache += sizeof(*header); |
| 172 | |
| 173 | /* Copy the FSP binary from the SMM region back into RAM */ |
| 174 | memcpy(header->start, fsp_cache, header->size); |
| 175 | |
| 176 | /* Return the FSP_INFO_HEADER address */ |
| 177 | return header->fih; |
| 178 | } |
| 179 | |
Aaron Durbin | 39bdb0b | 2015-08-04 23:59:43 -0500 | [diff] [blame] | 180 | static void fsp_run_silicon_init(int is_s3_wakeup) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 181 | { |
| 182 | FSP_INFO_HEADER *fsp_info_header; |
| 183 | FSP_SILICON_INIT fsp_silicon_init; |
| 184 | SILICON_INIT_UPD *original_params; |
| 185 | SILICON_INIT_UPD silicon_init_params; |
| 186 | EFI_STATUS status; |
| 187 | UPD_DATA_REGION *upd_ptr; |
| 188 | VPD_DATA_REGION *vpd_ptr; |
| 189 | |
| 190 | /* Find the FSP image */ |
| 191 | fsp_info_header = fsp_get_fih(); |
| 192 | if (fsp_info_header == NULL) { |
| 193 | printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n"); |
| 194 | return; |
| 195 | } |
| 196 | print_fsp_info(fsp_info_header); |
| 197 | |
| 198 | /* Initialize the UPD values */ |
| 199 | vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset + |
| 200 | fsp_info_header->ImageBase); |
| 201 | printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr); |
| 202 | upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + |
| 203 | fsp_info_header->ImageBase); |
| 204 | printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr); |
| 205 | original_params = (void *)((u8 *)upd_ptr + |
| 206 | upd_ptr->SiliconInitUpdOffset); |
| 207 | memcpy(&silicon_init_params, original_params, |
| 208 | sizeof(silicon_init_params)); |
| 209 | soc_silicon_init_params(&silicon_init_params); |
| 210 | |
| 211 | /* Locate VBT and pass to FSP GOP */ |
| 212 | if (IS_ENABLED(CONFIG_GOP_SUPPORT)) |
Aaron Durbin | 39bdb0b | 2015-08-04 23:59:43 -0500 | [diff] [blame] | 213 | load_vbt(is_s3_wakeup, &silicon_init_params); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 214 | mainboard_silicon_init_params(&silicon_init_params); |
| 215 | |
| 216 | /* Display the UPD data */ |
| 217 | if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) |
| 218 | soc_display_silicon_init_params(original_params, |
| 219 | &silicon_init_params); |
| 220 | |
| 221 | /* Perform silicon initialization after RAM is configured */ |
| 222 | printk(BIOS_DEBUG, "Calling FspSiliconInit\n"); |
| 223 | fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase |
| 224 | + fsp_info_header->FspSiliconInitEntryOffset); |
| 225 | timestamp_add_now(TS_FSP_SILICON_INIT_START); |
| 226 | printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n", |
| 227 | &silicon_init_params, fsp_silicon_init); |
| 228 | status = fsp_silicon_init(&silicon_init_params); |
| 229 | timestamp_add_now(TS_FSP_SILICON_INIT_END); |
| 230 | printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); |
| 231 | |
| 232 | #if IS_ENABLED(CONFIG_DISPLAY_HOBS) |
| 233 | /* Verify the HOBs */ |
| 234 | const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; |
| 235 | void *hob_list_ptr = get_hob_list(); |
| 236 | int missing_hob = 0; |
| 237 | |
| 238 | if (hob_list_ptr == NULL) |
| 239 | die("ERROR - HOB pointer is NULL!\n"); |
| 240 | print_hob_type_structure(0, hob_list_ptr); |
| 241 | |
| 242 | /* |
| 243 | * Verify that FSP is generating the required HOBs: |
| 244 | * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 |
| 245 | * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit |
| 246 | * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit |
| 247 | * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit |
| 248 | * 7.5: EFI_PEI_GRAPHICS_INFO_HOB verified below, |
| 249 | * if the ImageAttribute bit is set |
| 250 | * FSP_SMBIOS_MEMORY_INFO HOB verified by raminit |
| 251 | */ |
| 252 | if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) && |
| 253 | !get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) { |
| 254 | printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n"); |
| 255 | missing_hob = 1; |
| 256 | } |
| 257 | if (missing_hob) |
| 258 | die("ERROR - Missing one or more required FSP HOBs!\n"); |
| 259 | #endif |
| 260 | |
| 261 | soc_after_silicon_init(); |
| 262 | } |
| 263 | |
| 264 | static void fsp_cache_save(void) |
| 265 | { |
| 266 | const struct cbmem_entry *fsp_entry; |
| 267 | FSP_INFO_HEADER *fih; |
| 268 | |
| 269 | fsp_entry = cbmem_entry_find(CBMEM_ID_REFCODE); |
| 270 | |
| 271 | if (fsp_entry == NULL) { |
| 272 | printk(BIOS_ERR, "ERROR: FSP not found in CBMEM.\n"); |
| 273 | return; |
| 274 | } |
| 275 | |
| 276 | fih = fsp_get_fih(); |
| 277 | |
| 278 | if (fih == NULL) { |
| 279 | printk(BIOS_ERR, "ERROR: No FIH found.\n"); |
| 280 | return; |
| 281 | } |
| 282 | |
| 283 | soc_save_support_code(cbmem_entry_start(fsp_entry), |
| 284 | cbmem_entry_size(fsp_entry), fih); |
| 285 | } |
| 286 | |
| 287 | static int fsp_find_and_relocate(void) |
| 288 | { |
Aaron Durbin | 22ea007 | 2015-08-05 10:17:33 -0500 | [diff] [blame] | 289 | struct prog fsp_prog = PROG_INIT(ASSET_REFCODE, "fsp.bin"); |
| 290 | struct region_device fsp_rdev; |
| 291 | uint32_t type = CBFS_TYPE_FSP; |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 292 | |
Aaron Durbin | 22ea007 | 2015-08-05 10:17:33 -0500 | [diff] [blame] | 293 | if (cbfs_boot_locate(&fsp_rdev, prog_name(&fsp_prog), &type)) { |
| 294 | printk(BIOS_ERR, "ERROR: Couldn't find fsp.bin in CBFS.\n"); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 295 | return -1; |
| 296 | } |
| 297 | |
Aaron Durbin | 22ea007 | 2015-08-05 10:17:33 -0500 | [diff] [blame] | 298 | if (fsp_relocate(&fsp_prog, &fsp_rdev)) { |
| 299 | printk(BIOS_ERR, "ERROR: FSP relocation failed.\n"); |
| 300 | return -1; |
| 301 | } |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 302 | |
Aaron Durbin | 22ea007 | 2015-08-05 10:17:33 -0500 | [diff] [blame] | 303 | /* FSP_INFO_HEADER is set as the program entry. */ |
| 304 | fsp_update_fih(prog_entry(&fsp_prog)); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 305 | |
| 306 | return 0; |
| 307 | } |
| 308 | |
| 309 | void intel_silicon_init(void) |
| 310 | { |
Aaron Durbin | 39bdb0b | 2015-08-04 23:59:43 -0500 | [diff] [blame] | 311 | int is_s3_wakeup = acpi_is_wakeup_s3(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 312 | |
Aaron Durbin | 39bdb0b | 2015-08-04 23:59:43 -0500 | [diff] [blame] | 313 | if (is_s3_wakeup) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 314 | printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); |
| 315 | fsp_update_fih(soc_restore_support_code()); |
| 316 | } else { |
| 317 | fsp_find_and_relocate(); |
| 318 | printk(BIOS_DEBUG, "FSP: Saving binary in cache\n"); |
| 319 | fsp_cache_save(); |
| 320 | } |
| 321 | |
Aaron Durbin | 39bdb0b | 2015-08-04 23:59:43 -0500 | [diff] [blame] | 322 | fsp_run_silicon_init(is_s3_wakeup); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 323 | } |
| 324 | |
| 325 | /* Initialize the UPD parameters for SiliconInit */ |
| 326 | __attribute__((weak)) void mainboard_silicon_init_params( |
| 327 | SILICON_INIT_UPD *params) |
| 328 | { |
| 329 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 330 | }; |
| 331 | |
| 332 | /* Display the UPD parameters for SiliconInit */ |
| 333 | __attribute__((weak)) void soc_display_silicon_init_params( |
| 334 | const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) |
| 335 | { |
| 336 | printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); |
| 337 | hexdump32(BIOS_SPEW, new, sizeof(*new)); |
| 338 | } |
| 339 | |
| 340 | /* Initialize the UPD parameters for SiliconInit */ |
| 341 | __attribute__((weak)) void soc_silicon_init_params(SILICON_INIT_UPD *params) |
| 342 | { |
| 343 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 344 | } |