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Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]1<!DOCTYPE html>
2<html>
3 <head>
4 <title>Development</title>
5 </head>
6 <body>
7
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]8<h1>Intel&reg; x86 coreboot/FSP Development Process</h1>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]9<p>
10 The x86 development process for coreboot is broken into the following components:
11</p>
12<ul>
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]13 <li>coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li>
14 <li>coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]15 <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li>
16</ul>
17<p>
18 The development process has two main phases:
19</p>
20<ol>
21 <li>Minimal coreboot; This phase is single threaded</li>
22 <li>Adding coreboot features</li>
23</ol>
24
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]25<h2>Minimal coreboot</h2>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]26<p>
27 The combined steps below describe how to bring up a minimal coreboot for a
28 system-on-a-chip (SoC) and a development board:
29</p>
30<table>
31 <tr bgcolor="#ffffc0">
32 <td>The initial coreboot steps are single threaded!
33 The initial minimal FSP development is also single threaded.
34 Progress can speed up by adding more developers after the minimal coreboot/FSP
35 implementation reaches the payload.
36 </td>
37 </tr>
38</table>
39<ol>
40 <li>Get the necessary tools:
41 <ul>
42 <li>Linux: Use your package manager to install m4 bison flex and the libcurses development
43 package.
44 <ul>
45 <li>Ubuntu or other Linux distribution that use apt, run:
46<pre><code>sudo apt-get install m4 bison flex libncurses5-dev
47</code></pre>
48 </li>
49 </ul>
50 </li>
51 </ul>
52 </li>
53 <li>Build the cross tools for i386:
54 <ul>
55 <li>Linux:
56<pre><code>make crossgcc-i386</code></pre>
57 To use multiple processors for the toolchain build (which takes a long time), use:
58<pre><code>make crossgcc-i386 CPUS=N</code></pre>
59 where N is the number of cores to use for the build.
60 </li>
61 </ul>
62 </li>
63 <li>Get something to build:
64 <ol type="A">
65 <li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
66 <li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li>
67 <li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li>
68 </ol>
69 </li>
70 <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li>
71 <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
Lee Leahy380e1672016-01-31 10:49:35 -0800[diff] [blame]72 <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]73 <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]74 <li>Enable the serial port
75 <ol type="A">
76 <li>Power on, enable and configure GPIOs for the
77 <a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a>
78 </li>
79 <li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a>
80 support to romstage
81 </li>
82 </ol>
83 </li>
84 <li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li>
Lee Leahyfcf776f2016-02-04 11:23:36 -0800[diff] [blame]85 <li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li>
86 <li>Enable DRAM:
87 <ol type="A">
88 <li>Implement the SoC
89 <a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a>
90 Support
91 </li>
92 <li>Implement the board support to read the
93 <a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a>
94 </li>
95 </ol>
96 </li>
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame]97 <li>
98 Implement the .init routine for the
99 <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
100 structure which calls FSP SiliconInit
101 </li>
102 <li>
103 Start ramstage's
104 <a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a>
105 to display the PCI vendor and device IDs
106 </li>
107 <li>
108 Disable the
109 <a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a>
110 </li>
111 <li>
112 Implement the
113 <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
114 </li>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]115</ol>
116
117
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]118
Lee Leahybf08da22016-02-20 17:48:35 -0800[diff] [blame]119<h2>Add coreboot Features</h2>
120<p>
121 Most of the coreboot development gets done in this phase. Implementation tasks in this
122 phase are easily done in parallel.
123</p>
124<ul>
125 <li>Payload and OS Features:
126 <ul>
127 <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li>
Lee Leahy4ee073d2016-02-28 06:22:47 -0800[diff] [blame]128 <li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li>
Lee Leahybf08da22016-02-20 17:48:35 -0800[diff] [blame]129 </ul>
130 </li>
131</ul>
132
133
134
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]135<hr>
136<table border="1">
137 <tr bgcolor="#c0ffc0">
138 <th colspan=3><h1>Features</h1></th>
139 </tr>
140 <tr bgcolor="#c0ffc0">
141 <th>SoC</th>
142 <th>Where</th>
143 <th>Testing</th>
144 </tr>
145 <tr>
Lee Leahy4ee073d2016-02-28 06:22:47 -0800[diff] [blame]146 <td>8254 Programmable Interval Timer</td>
147 <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
148 <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
149 </tr>
150 <tr>
151 <td>8259 Programmable Interrupt Controller</td>
152 <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
153 <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
154 </tr>
155 <tr>
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]156 <td>Cache-as-RAM</td>
157 <td>
158 <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a>
159 FSP binary:
160 <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br>
161 Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a>
162 called from
163 <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br>
164 Disable: FSP 1.1 TempRamExit called from
165 <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
166 </td>
167 <td>FindFSP: POST code 0x90
168 (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
169 is displayed<br>
170 Enable: POST code
171 <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
172 is displayed<br>
173 Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
174 </td>
175 </tr>
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame]176 <tr>
177 <td>Memory Map</td>
178 <td>
179 Implement a device driver for the
180 <a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a>
181 </td>
182 <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
183 </tr>
184 <tr>
185 <td>PCI Device Support</td>
186 <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>
187 <td>The device is detected by coreboot and usable by the payload</td>
188 </tr>
189 <tr>
190 <td>Ramstage state machine</td>
191 <td>
192 Implement the chip and domain operations to start the
193 <a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a>
194 processing
195 </td>
196 <td>
197 During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
198 for the PCI devices on the bus.
199 </td>
200 </tr>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]201
202
203 <tr bgcolor="#c0ffc0">
204 <th>Board</th>
205 <th>Where</th>
206 <th>Testing</th>
207 </tr>
208 <tr>
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame]209 <td>Device Tree</td>
210 <td>
211 <a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting
212 the device tree processing<br>
213 <a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br>
214 Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a>
215 <td>
216 List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br>
217 Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br>
218 Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
219 </td>
220 </tr>
221 <tr>
Lee Leahyfcf776f2016-02-04 11:23:36 -0800[diff] [blame]222 <td>DRAM</td>
223 <td>
224 Load SPD data: src/soc/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br>
225 UPD Setup:
226 <ul>
227 <li>src/soc&lt;Vendor&gt;//&lt;Chip Family&gt;/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li>
228 <li>src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li>
229 </ul>
230 FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l126">raminit.c</a>
231 </td>
232 <td>Select the following Kconfig values
233 <ul>
234 <li>DISPLAY_HOBS</li>
235 <li>DISPLAY_UPD_DATA</li>
236 </ul>
237 Testing successful if:
238 <ul>
239 <li>MemoryInit UPD values are correct</li>
240 <li>MemoryInit returns 0 (success) and</li>
241 <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
242 is not displayed
243 </li>
244 </ul>
245 </td>
246 </tr>
247 <tr>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]248 <td>Serial Port</td>
249 <td>
250 SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br>
251 Enable: src/soc/mainboard/&lt;Board&gt;/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a>
252 </td>
253 <td>Debug serial output works</td>
254 </tr>
255
256
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]257 <tr bgcolor="#c0ffc0">
Lee Leahybf08da22016-02-20 17:48:35 -0800[diff] [blame]258 <th>Payload</th>
259 <th>Where</th>
260 <th>Testing</th>
261 </tr>
262 <tr>
263 <td>ACPI Tables</td>
264 <td>
265 SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br>
266 </td>
267 <td>Verified by payload or OS</td>
268 </tr>
269
270
271 <tr bgcolor="#c0ffc0">
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]272 <th>FSP</th>
273 <th>Where</th>
274 <th>Testing</th>
275 </tr>
276 <tr>
277 <td>TempRamInit</td>
278 <td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td>
279 <td>FSP binary found: POST code 0x90
280 (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
281 is displayed<br>
282 TempRamInit successful: POST code
283 <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
284 is displayed<br>
285 </td>
286 </tr>
Lee Leahyfcf776f2016-02-04 11:23:36 -0800[diff] [blame]287 <tr>
288 <td>MemoryInit</td>
289 <td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br>
290 <a target="_blank" href="Board/board.html#SpdData">Board</a> support<br>
291 </td>
292 <td>Select the following Kconfig values
293 <ul>
294 <li>DISPLAY_HOBS</li>
295 <li>DISPLAY_UPD_DATA</li>
296 </ul>
297 Testing successful if:
298 <ul>
299 <li>MemoryInit UPD values are correct</li>
300 <li>MemoryInit returns 0 (success) and</li>
301 <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
302 is not displayed
303 </li>
304 </ul>
305 </td>
306 </tr>
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame]307 <tr>
Lee Leahybf08da22016-02-20 17:48:35 -0800[diff] [blame]308 <td>TempRamExit</td>
309 <td>src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
310 <td>Post code 0x91
311 (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>)
312 is displayed before calling TempRamExit by
313 <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>,
314 CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and
315 Post code 0x39 is displayed by
316 <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br>
317 </td>
318 </tr>
319 <tr>
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame]320 <td>SiliconInit</td>
321 <td>
322 Implement the .init routine for the
323 <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure
324 </td>
325 <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td>
326 </tr>
327 <tr>
328 <td>FspNotify</td>
329 <td>
330 The code which calls FspNotify is located in
331 src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
332 The fsp_notify_boot_state_callback routine is called three times as specified
333 by the BOOT_STATE_INIT_ENTRY macros below the routine.
334 </td>
335 <td>
336 The FspNotify routines are called during:
337 <ul>
338 <li>BS_DEV_RESOURCES - on exit</li>
339 <li>BS_PAYLOAD_LOAD - on exit</li>
340 <li>BS_OS_RESUME - on entry (S3 resume)</li>
341 </ul>
342 </td>
343 </tr>
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]344</table>
345
346
347
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]348<hr>
Lee Leahy4ee073d2016-02-28 06:22:47 -0800[diff] [blame]349<p>Modified: 24 February 2016</p>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]350 </body>
351</html>