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Steven Sherkd9de6c42013-04-11 08:40:57 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
Dave Frodin0240f942014-06-05 12:01:36 -06005 * Copyright (C) 2014 Sage Electronic Engineering, LLC
Steven Sherkd9de6c42013-04-11 08:40:57 -06006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Steven Sherkd9de6c42013-04-11 08:40:57 -060016 */
17
Dave Frodinda2daef2014-06-09 12:33:24 -060018#ifndef SUPERIO_NUVOTON_NCT5104D_H
19#define SUPERIO_NUVOTON_NCT5104D_H
Steven Sherkd9de6c42013-04-11 08:40:57 -060020
Kyösti Mälkki3855c012019-03-03 08:45:19 +020021#include <device/pnp_type.h>
22
Dave Frodin29179f02014-06-12 16:28:21 -060023/* SIO global configuration */
24#define IRQ_TYPE_SEL_CR10 0x10 /* UARTA,UARTB */
25#define IRQ_TYPE_SEL_CR11 0x11 /* SMI,UARTC,UARTD,WDTO */
26#define GLOBAL_OPTION_CR26 0x26
27#define CR26_LOCK_REG (1 << 4) /* required to access CR10/CR11 */
28
Piotr Kleinschmidtb52f7c72019-09-19 16:25:56 +020029/* LDN 0x07 specific registers */
30#define NCT5104D_GPIO0_IO 0xE0
31#define NCT5104D_GPIO1_IO 0xE4
32#define NCT5104D_GPIO6_IO 0xF8
33
34/* LDN 0x0F specific registers */
35#define NCT5104D_GPIO0_PP_OD 0xE0
36#define NCT5104D_GPIO1_PP_OD 0xE1
37#define NCT5104D_GPIO6_PP_OD 0xE6
38
Steven Sherkd9de6c42013-04-11 08:40:57 -060039/* Logical Device Numbers (LDN). */
Dave Frodin0240f942014-06-05 12:01:36 -060040#define NCT5104D_FDC 0x00 /* FDC - not pinned out */
41#define NCT5104D_SP1 0x02 /* UARTA */
42#define NCT5104D_SP2 0x03 /* UARTB */
43#define NCT5104D_GPIO_WDT 0x08 /* GPIO WDT Interface */
44#define NCT5104D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select */
45#define NCT5104D_SP3 0x10 /* UARTC */
46#define NCT5104D_SP4 0x11 /* UARTD */
47#define NCT5104D_PORT80 0x14 /* PORT 80 */
Steven Sherkd9de6c42013-04-11 08:40:57 -060048
49/* Virtual Logical Device Numbers (LDN) */
50#define NCT5104D_GPIO_V 0x07 /* GPIO - 0,1,6 Interface */
51
52/* Virtual devices sharing the enables are encoded as follows:
53 VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
54*/
55#define NCT5104D_GPIO0 ((0 << 8) | NCT5104D_GPIO_V)
56#define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V)
57#define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V)
58
Edward O'Callaghan85836c22014-07-09 20:26:25 +100059void nct5104d_enable_uartd(pnp_devfn_t dev);
Dave Frodinda2daef2014-06-09 12:33:24 -060060
61#endif /* SUPERIO_NUVOTON_NCT5104D_H */