blob: 0f356e477596621770886956b7fda748ff2fcb72 [file] [log] [blame]
Nick Vaccaro02558042017-12-22 23:07:58 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
13 * GNU General Public License for more details.
14 */
15
16#include <baseboard/gpio.h>
17#include <baseboard/variants.h>
18
19/* Pad configuration in ramstage */
20static const struct pad_config gpio_table[] = {
21/* RCIN# */ PAD_NC(GPP_A0, NONE), /* PCH_CSI_GPIO1 */
22/* ESPI_IO0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF2), /* ESPI_IO0_R */
23/* ESPI_IO1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF2), /* ESPI_IO0_R */
24/* ESPI_IO2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF2), /* ESPI_IO2_R */
25/* ESPI_IO3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF2), /* ESPI_IO3_R */
26/* ESPI_CS# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF2), /* ESPI_CS_L */
27/* SERIRQ */ PAD_NC(GPP_A6, NONE),
28/* PIRQA# */ PAD_NC(GPP_A7, NONE),
29/* CLKRUN# */ PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* EC_IN_RW_OD */
30/* ESPI_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), /* ESPI_CLK_R */
31/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),
Vincent Palatin9d1eb292018-01-16 08:22:45 +010032/* PME# */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* PCH_FP_PWR_EN */
Nick Vaccaro02558042017-12-22 23:07:58 -080033/* BM_BUSY# */ PAD_CFG_GPI(GPP_A12, NONE, DEEP), /* FPMCU_INT */
34/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN_L */
35/* ESPI_RESET# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2), /* ESPI_RESET_L */
36/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SUSACK_L */
37/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
38/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
39/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
40/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
41/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
42/* ISH_GP3 */ PAD_CFG_GPO(GPP_A21, 0, DEEP), /* PCH_FPMCU_BOOT0 */
Vincent Palatina25283d2018-02-14 11:51:14 +010043/* ISH_GP4 */ PAD_CFG_GPI_APIC(GPP_A22, NONE, DEEP, LEVEL,
44 NONE), /* FPMCU_INT */
Nick Vaccaro02558042017-12-22 23:07:58 -080045/* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* PCH_FPMCU_RST_ODL */
46/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */
47/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */
48/* VRALERT# */ PAD_NC(GPP_B2, NONE),
49/* CPU_GP2 */ PAD_NC(GPP_B3, NONE),
50/* CPU_GP3 */ PAD_NC(GPP_B4, NONE),
51/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE),
52/* SRCCLKREQ1# */ PAD_NC(GPP_B6, NONE),
Nick Vaccaro896b6ab2018-01-21 22:26:33 -080053/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE),
Nick Vaccaro02558042017-12-22 23:07:58 -080054/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP,
55 NF1), /* PCIE_NVME_CLKREQ_ODL */
56/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE),
57/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
58/* EXT_PWR_GATE# */
59/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_SO_L */
60/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST_L */
61/* SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), /* GPP_B14_STRAP */
62#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)
63/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,
64 NF1), /* H1_SLAVE_SPI_CS_L */
65/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,
66 NF1), /* H1_SLAVE_SPI_CLK */
67/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
68 NF1), /* H1_SLAVE_SPI_MISO_R */
69/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
70 NF1), /* H1_SLAVE_SPI_MOSI_R */
71#else
72/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE),
73/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
74/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
75/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
76#endif
77/* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP,
78 NF1), /* PCH_FPMCU_SPI_CS_L */
79/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP,
80 NF1), /* PCH_FPMCU_SPI_CLK */
81/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP,
82 NF1), /* PCH_FPMCU_SPI_MISO_R */
83/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP,
84 NF1), /* PCH_FPMCU_SPI_MOSI_R */
85/* SML1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* GPP_B23_STRAP */
86/* SMBCLK */ PAD_NC(GPP_C0, NONE),
Nick Vaccaro896b6ab2018-01-21 22:26:33 -080087/* SMBDATA */ PAD_NC(GPP_C1, NONE),
Nick Vaccaro02558042017-12-22 23:07:58 -080088/* SMBALERT# */ PAD_CFG_GPI(GPP_C2, NONE, DEEP), /* GPP_C2_STRAP */
Gwendal Grignouc3d4c422018-03-07 13:44:16 -080089/* SML0CLK */ PAD_CFG_GPI_APIC(GPP_C3, NONE, DEEP, LEVEL,
90 NONE), /* PCH_SAR1_INT_L */
91/* SML0DATA */ PAD_CFG_GPI_APIC(GPP_C4, NONE, DEEP, LEVEL,
92 NONE), /* PCH_SAR0_INT_L */
Nick Vaccaro02558042017-12-22 23:07:58 -080093/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* GPP_C5_STRAP */
Nick Vaccaroa894ebb2018-03-08 17:49:53 -080094/* SM1CLK */ PAD_NC(GPP_C6, NONE),
Nick Vaccaro02558042017-12-22 23:07:58 -080095/* SM1DATA */ PAD_NC(GPP_C7, NONE),
96/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP,
97 NF1), /* UART_PCH_RX_DEBUG_TX */
98/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP,
99 NF1), /* UART_PCH_TX_DEBUG_RX */
Nick Vaccaroc92f1352018-02-01 13:36:49 -0800100/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* PP3300_TOUCH_EN */
Nick Vaccaro02558042017-12-22 23:07:58 -0800101/* UART0_CTS# */ PAD_NC(GPP_C11, NONE),
Caveh Jalali6de0cd22018-01-17 17:40:27 -0800102/* Only P0 boards need an internal pullup */
103/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, UP_20K, DEEP, EDGE_SINGLE,
104 INVERT), /* H1_PCH_INT_ODL */
Nick Vaccaro02558042017-12-22 23:07:58 -0800105/* UART1_TXD */ PAD_NC(GPP_C13, NONE),
Nick Vaccaroc92f1352018-02-01 13:36:49 -0800106/* UART1_RTS# */ PAD_CFG_GPI_APIC(GPP_C14, NONE, DEEP, LEVEL,
Nick Vaccaro02558042017-12-22 23:07:58 -0800107 NONE), /* TOUCHSCREEN_INT_ODL */
108/* UART1_CTS# */ PAD_NC(GPP_C15, NONE),
109/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP,
110 NF1), /* PCH_TOUCHSCREEN_I2C0_SDA */
111/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP,
112 NF1), /* PCH_TOUCHSCREEN_I2C0_SCL */
113/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP,
114 NF1), /* PCH_DISPLAY_SAR1_I2C1_SDA */
115/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP,
116 NF1), /* PCH_DISPLAY_SAR1_I2C1_SCL */
117/* UART2_RXD */ PAD_NC(GPP_C20, NONE),
118/* UART2_TXD */ PAD_NC(GPP_C21, NONE),
119/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),
120/* UART2_CTS# */ PAD_NC(GPP_C23, NONE),
121/* SPI1_CS# */ PAD_CFG_GPI(GPP_D0, NONE, DEEP), /* PCH_MEM_STRAP3 */
122/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),
123/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),
124/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* PCH_MEM_STRAP0 */
125/* FASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* FCAM_MCLK */
126/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
127/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
128/* ISH_I2C1_SDA */ PAD_CFG_GPO(GPP_D7, 1, DEEP), /* FCAM_RST_L */
Sathyanarayana Nujella206821e2018-01-19 10:23:05 -0800129/* ISH_I2C1_SCL */ PAD_CFG_GPO(GPP_D8, 1, DEEP), /* DMIC_PWR_EN */
130/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE),
131/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* FCAM_PWR_EN */
Nick Vaccaro02558042017-12-22 23:07:58 -0800132/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE),
133/* ISH_SPI_MOSI */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), /* GPP_D12_STRAP */
134/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), /* ISH_UART_RX */
135/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), /* ISH_UART_TX */
136/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TOUCHSCREEN_RST_ODL */
Sathyanarayana Nujella206821e2018-01-19 10:23:05 -0800137/* ISH_UART0_CTS# */ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* SPKR_HWRST_L */
Nick Vaccaro02558042017-12-22 23:07:58 -0800138/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP,
139 NF1), /* DB0_PCH_DMIC_CLK_R */
140/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP,
141 NF1), /* DB0TX_PCHRX_DMIC_DATA */
142/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),
143/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),
144/* SPI1_IO2 */ PAD_CFG_GPI(GPP_D21, NONE, DEEP), /* PCH_MEM_STRAP1 */
145/* SPI1_IO3 */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), /* PCH_MEM_STRAP2 */
146/* I2S_MCLK */
147/* SATAXPCI0 */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* RCAM_PWR_EN */
148/* SATAXPCIE1 */ PAD_CFG_GPO(GPP_E1, 1, DEEP), /* RCAM_RST_L */
149/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE),
150/* CPU_GP0 */ PAD_NC(GPP_E3, NONE),
151/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE),
152/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE),
153/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),
154/* CPU_GP1 */ PAD_NC(GPP_E7, NONE),
155/* SATALED# */ PAD_NC(GPP_E8, NONE),
Nick Vaccaro896b6ab2018-01-21 22:26:33 -0800156/* USB2_OCO# */ PAD_NC(GPP_E9, NONE),
157/* USB2_OC1# */ PAD_NC(GPP_E10, NONE),
Nick Vaccaro02558042017-12-22 23:07:58 -0800158/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,
159 NF1), /* USB_C0_OC_ODL */
160/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,
161 NF1), /* USB_C1_OC_ODL */
162/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,
163 NF1), /* EC_USB_C0_HPD */
164/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,
165 NF1), /* EC_USB_C1_HPD */
166/* DDPD_HPD2 */ PAD_CFG_NF(GPP_E15, NONE, DEEP,
167 NF1), /* EC_USB_C2_HPD */
168/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),
169/* EDP_HPD */
170/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE),
171/* DDPB_CTRLDATA */ PAD_CFG_GPI(GPP_E19, NONE, DEEP), /* GPP_E19_STRAP */
172/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
173/* DDPC_CTRLDATA */ PAD_CFG_GPI(GPP_E21, NONE, DEEP), /* GPP_E21_STRAP */
174/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
175/* DDPD_CTRLDATA */ PAD_CFG_GPI(GPP_E23, NONE, DEEP), /* GPP_E23_STRAP */
176/* I2S2_SFRM */ PAD_CFG_GPO(GPP_F1, 0, DEEP),
177 /* WWAN_RESET_1V8_ODL */
178/* I2S2_TXD */ PAD_NC(GPP_F2, NONE),
179/* I2S2_RXD */ PAD_NC(GPP_F3, NONE),
180/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_DT_R */
181/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* CNV_BRI_RSP */
182/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_RGI_DT_R */
183/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* CNV_RGI_RSP */
184/* I2C4_SDA */ PAD_NC(GPP_F8, NONE),
185/* I2C4_SCL */ PAD_NC(GPP_F9, NONE),
186/* I2C5_SDA */ PAD_CFG_GPI(GPP_F10, NONE,
187 DEEP), /* OPVR_MCIVR_BREAK_L */
188/* I2C5_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* EMMC_CMD */
189/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DAT0 */
190/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DAT1 */
191/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), /* EMMC_DAT2 */
192/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* EMMC_DAT3 */
193/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* EMMC_DAT4 */
194/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* EMMC_DAT5 */
195/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* EMMC_DAT6 */
196/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* EMMC_DAT7 */
197/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */
198/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */
199/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* EMMC_RST_ODL */
200/* RSVD */
201/* SD_CMD */ PAD_NC(GPP_G0, NONE),
202/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
203/* SD_DATA1 */ PAD_NC(GPP_G2, NONE),
204/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
205/* SD_DATA3 */ PAD_NC(GPP_G4, NONE),
206/* SD_CD# */ PAD_NC(GPP_G5, NONE),
207/* SD_CLK */ PAD_NC(GPP_G6, NONE),
208/* SD_WP */ PAD_NC(GPP_G7, NONE),
209/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),
210/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP,
211 NF3), /* CNV_RF_RESET_L */
212/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* WLAN_CLKREQ0 */
213/* I2S2_RXD */ PAD_NC(GPP_H3, NONE),
Nick Vaccaroa894ebb2018-03-08 17:49:53 -0800214/* I2C2_SDA */ PAD_NC(GPP_H4, NONE),
215/* I2C2_SCL */ PAD_NC(GPP_H5, NONE),
Nick Vaccaro02558042017-12-22 23:07:58 -0800216/* I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP,
217 NF1), /* PCH_AUDIO_I2C3_SDA */
218/* I2C3_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP,
219 NF1), /* PCH_AUDIO_I2C3_SCL */
220/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP,
221 NF1), /* PCH_FCAM_I2C4_SDA */
222/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP,
223 NF1), /* PCH_FCAM_I2C4_SCL */
224/* I2C5_SDA */ PAD_CFG_NF(GPP_H10, NONE, DEEP,
225 NF1), /* PCH_RCAM_SAR0_I2C5_SDA */
226/* I2C5_SCL */ PAD_CFG_NF(GPP_H11, NONE, DEEP,
227 NF1), /* PCH_RCAM_SAR0_I2C5_SCL */
Nick Vaccaro9e17e112018-01-21 22:11:52 -0800228/* M2_SKT2_CFG0 */ PAD_CFG_GPI(GPP_H12, NONE, DEEP), /* PCH_WP_OD */
Nick Vaccaro02558042017-12-22 23:07:58 -0800229/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
230/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
231/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE),
232/* DDPF_CTRLCLK */
233/* DPPF_CTRLDATA */
234/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP,
235 NF1), /* CPU_C10_GATE_PCH_L */
236/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE),
237/* IMGCLKOUT1 */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* RCAM_MCLK */
238/* GPP_H21 */ PAD_CFG_GPI(GPP_H21, NONE, DEEP), /* H21_STRAP */
239/* GPP_H22 */ PAD_NC(GPP_H22, NONE),
240/* GPP_H23 */ PAD_CFG_GPI(GPP_H23, NONE, DEEP), /* GPP_H23 */
241
242/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW_L */
243/* ACPRESENT */ PAD_NC(GPD1, NONE),
Nick Vaccarof46fca42018-01-11 11:24:32 -0800244/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_ODL */
Nick Vaccaro02558042017-12-22 23:07:58 -0800245/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP,
246 NF1), /* EC_PCH_PWR_BTN_ODL */
247/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3_L */
248/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4_L */
249/* SLP_A# */ PAD_NC(GPD6, NONE),
250/* RSVD */ PAD_CFG_GPI(GPD7, NONE, DEEP), /* DPD7_Strap */
251/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* PCH_SUSCLK */
252/* SLP_WLAN# */ PAD_NC(GPD9, NONE),
253/* SLP_S5# */ PAD_NC(GPD10, NONE),
254/* LANPHYC */ PAD_NC(GPD11, NONE),
255};
256
257/* Early pad configuration in bootblock */
258static const struct pad_config early_gpio_table[] = {
259#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)
260/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,
261 NF1), /* PCH_SPI_H1_3V3_CS_L */
262/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,
263 NF1), /* PCH_SPI_H1_3V3_CLK */
264/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
265 NF1), /* PCH_SPI_H1_3V3_MISO */
266/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
267 NF1), /* PCH_SPI_H1_3V3_MOSI */
Nick Vaccaro2baf49f2017-12-20 16:48:17 -0800268#else
269/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE),
270/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
271/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
272/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
Nick Vaccaro02558042017-12-22 23:07:58 -0800273#endif
Caveh Jalali6de0cd22018-01-17 17:40:27 -0800274/* Only P0 boards need an internal pullup */
275/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, UP_20K, DEEP, EDGE_SINGLE,
276 INVERT), /* H1_PCH_INT_ODL */
Nick Vaccaro02558042017-12-22 23:07:58 -0800277};
278
279const struct pad_config *variant_gpio_table(size_t *num)
280{
281 *num = ARRAY_SIZE(gpio_table);
282 return gpio_table;
283}
284
285const struct pad_config *variant_early_gpio_table(size_t *num)
286{
287 *num = ARRAY_SIZE(early_gpio_table);
288 return early_gpio_table;
289}