| Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | /* DefinitionBlock Statement */ |
| 18 | DefinitionBlock ( |
| 19 | "DSDT.AML", /* Output filename */ |
| 20 | "DSDT", /* Signature */ |
| 21 | 0x02, /* DSDT Revision, needs to be 2 for 64bit */ |
| 22 | "ASUS ", /* OEMID */ |
| 23 | "COREBOOT", /* TABLE ID */ |
| 24 | 0x00010001 /* OEM Revision */ |
| 25 | ) |
| 26 | { /* Start of ASL file */ |
| 27 | /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ |
| 28 | |
| 29 | /* Globals for the platform */ |
| 30 | #include "acpi/mainboard.asl" |
| 31 | |
| 32 | /* PCI IRQ mapping for the Southbridge */ |
| 33 | #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> |
| 34 | |
| 35 | /* Describe the processor tree (\_PR) */ |
| 36 | #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> |
| 37 | |
| 38 | /* Describe the supported Sleep States for this Southbridge */ |
| 39 | #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl> |
| 40 | |
| 41 | /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ |
| 42 | #include "acpi/sleep.asl" |
| 43 | |
| 44 | Scope(\_SB) { |
| 45 | /* global utility methods expected within the \_SB scope */ |
| 46 | #include <arch/x86/acpi/globutil.asl> |
| 47 | |
| 48 | /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ |
| 49 | #include "acpi/routing.asl" |
| 50 | |
| 51 | Device(PWRB) { |
| 52 | Name(_HID, EISAID("PNP0C0C")) |
| 53 | Name(_UID, 0xAA) |
| 54 | Name(_PRW, Package () {3, 0x04}) |
| 55 | Name(_STA, 0x0B) |
| 56 | } |
| 57 | |
| 58 | Device(PCI0) { |
| 59 | /* Describe the AMD Northbridge */ |
| 60 | #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> |
| 61 | |
| 62 | /* Describe the AMD Fusion Controller Hub Southbridge */ |
| 63 | #include <southbridge/amd/agesa/hudson/acpi/fch.asl> |
| 64 | |
| 65 | /** |
| 66 | * TODO: The devices listed here (SBR0 and SBR1) do not appear to |
| 67 | * be referenced anywhere and could possibly be removed. |
| 68 | */ |
| 69 | Device(SBR0) { /* PCIe 1x SB */ |
| 70 | Name(_ADR, 0x00150000) |
| 71 | Name(_PRW, Package() {0x18, 4}) |
| 72 | Method(_PRT,0) { |
| 73 | If(PMOD){ Return(ABR0) } /* APIC mode */ |
| 74 | Return (PBR0) /* PIC mode */ |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | Device(SBR1) { /* Onboard network */ |
| 79 | Name(_ADR, 0x00150001) |
| 80 | Name(_PRW, Package() {0x18, 4}) |
| 81 | Method(_PRT, 0) { |
| 82 | If(PMOD){ Return(ABR1) } /* APIC mode */ |
| 83 | Return (PBR1) /* PIC mode */ |
| 84 | } |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | /* Describe PCI INT[A-H] for the Southbridge */ |
| 89 | #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> |
| 90 | |
| 91 | } /* End Scope(_SB) */ |
| 92 | |
| 93 | /* Describe SMBUS for the Southbridge */ |
| 94 | #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> |
| 95 | |
| 96 | /* Define the General Purpose Events for the platform */ |
| 97 | #include "acpi/gpe.asl" |
| 98 | |
| 99 | /* Define the Thermal zones and methods for the platform */ |
| 100 | #include "acpi/thermal.asl" |
| 101 | |
| 102 | /* Define the System Indicators for the platform */ |
| 103 | #include "acpi/si.asl" |
| 104 | |
| 105 | } |
| 106 | /* End of ASL file */ |