Renze Nicolai | a688b7c | 2016-11-18 23:08:13 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | /* Routing is in System Bus scope */ |
| 18 | Name(PR0, Package(){ |
| 19 | /* NB devices */ |
| 20 | /* Bus 0, Dev 0 - F15 Host Controller */ |
| 21 | Package(){0x0000FFFF, 0, INTA, 0 }, |
| 22 | Package(){0x0000FFFF, 1, INTB, 0 }, |
| 23 | Package(){0x0000FFFF, 2, INTC, 0 }, |
| 24 | Package(){0x0000FFFF, 3, INTD, 0 }, |
| 25 | |
| 26 | /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ |
| 27 | Package(){0x0001FFFF, 0, INTB, 0 }, |
| 28 | Package(){0x0001FFFF, 1, INTC, 0 }, |
| 29 | |
| 30 | /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ |
| 31 | Package(){0x0002FFFF, 0, INTC, 0 }, |
| 32 | Package(){0x0002FFFF, 1, INTD, 0 }, |
| 33 | Package(){0x0002FFFF, 2, INTA, 0 }, |
| 34 | Package(){0x0002FFFF, 3, INTB, 0 }, |
| 35 | |
| 36 | /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ |
| 37 | |
| 38 | /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ |
| 39 | Package(){0x0004FFFF, 0, INTA, 0 }, |
| 40 | Package(){0x0004FFFF, 1, INTB, 0 }, |
| 41 | Package(){0x0004FFFF, 2, INTC, 0 }, |
| 42 | Package(){0x0004FFFF, 3, INTD, 0 }, |
| 43 | |
| 44 | /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ |
| 45 | /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ |
| 46 | /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ |
| 47 | /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ |
| 48 | |
| 49 | /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ |
| 50 | Package(){0x0014FFFF, 0, INTA, 0 }, |
| 51 | Package(){0x0014FFFF, 1, INTB, 0 }, |
| 52 | Package(){0x0014FFFF, 2, INTC, 0 }, |
| 53 | Package(){0x0014FFFF, 3, INTD, 0 }, |
| 54 | |
| 55 | /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 |
| 56 | * EHCI @ func 2 */ |
| 57 | Package(){0x0012FFFF, 0, INTC, 0 }, |
| 58 | Package(){0x0012FFFF, 1, INTB, 0 }, |
| 59 | |
| 60 | Package(){0x0013FFFF, 0, INTC, 0 }, |
| 61 | Package(){0x0013FFFF, 1, INTB, 0 }, |
| 62 | |
| 63 | Package(){0x0016FFFF, 0, INTC, 0 }, |
| 64 | Package(){0x0016FFFF, 1, INTB, 0 }, |
| 65 | |
| 66 | /* SB devices */ |
| 67 | /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ |
| 68 | Package(){0x0010FFFF, 0, INTC, 0 }, |
| 69 | Package(){0x0010FFFF, 1, INTB, 0 }, |
| 70 | |
| 71 | /* Bus 0, Dev 17 - SATA controller */ |
| 72 | Package(){0x0011FFFF, 0, INTD, 0 }, |
| 73 | |
| 74 | /* Bus 0, Dev 21 Pcie Bridge */ |
| 75 | Package(){0x0015FFFF, 0, INTA, 0 }, |
| 76 | Package(){0x0015FFFF, 1, INTB, 0 }, |
| 77 | Package(){0x0015FFFF, 2, INTC, 0 }, |
| 78 | Package(){0x0015FFFF, 3, INTD, 0 }, |
| 79 | }) |
| 80 | |
| 81 | Name(APR0, Package(){ |
| 82 | /* NB devices in APIC mode */ |
| 83 | /* Bus 0, Dev 0 - F15 Host Controller */ |
| 84 | Package(){0x0000FFFF, 0, 0, 16 }, |
| 85 | Package(){0x0000FFFF, 1, 0, 17 }, |
| 86 | Package(){0x0000FFFF, 2, 0, 18 }, |
| 87 | Package(){0x0000FFFF, 3, 0, 19 }, |
| 88 | |
| 89 | /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ |
| 90 | Package(){0x0001FFFF, 0, 0, 17 }, |
| 91 | Package(){0x0001FFFF, 1, 0, 18 }, |
| 92 | |
| 93 | /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ |
| 94 | Package(){0x0002FFFF, 0, 0, 18 }, |
| 95 | Package(){0x0002FFFF, 1, 0, 19 }, |
| 96 | Package(){0x0002FFFF, 2, 0, 16 }, |
| 97 | Package(){0x0002FFFF, 3, 0, 17 }, |
| 98 | |
| 99 | /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ |
| 100 | |
| 101 | /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ |
| 102 | Package(){0x0004FFFF, 0, 0, 16 }, |
| 103 | Package(){0x0004FFFF, 1, 0, 17 }, |
| 104 | Package(){0x0004FFFF, 2, 0, 18 }, |
| 105 | Package(){0x0004FFFF, 3, 0, 19 }, |
| 106 | |
| 107 | /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ |
| 108 | /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ |
| 109 | /* Bus 0, Dev 7 - PCIe Bridge for network card */ |
| 110 | /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ |
| 111 | |
| 112 | /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ |
| 113 | Package(){0x0014FFFF, 0, 0, 16 }, |
| 114 | Package(){0x0014FFFF, 1, 0, 17 }, |
| 115 | Package(){0x0014FFFF, 2, 0, 18 }, |
| 116 | Package(){0x0014FFFF, 3, 0, 19 }, |
| 117 | |
| 118 | /* SB devices in APIC mode */ |
| 119 | /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 |
| 120 | * EHCI @ func 2 */ |
| 121 | Package(){0x0012FFFF, 0, 0, 18 }, |
| 122 | Package(){0x0012FFFF, 1, 0, 17 }, |
| 123 | |
| 124 | Package(){0x0013FFFF, 0, 0, 18 }, |
| 125 | Package(){0x0013FFFF, 1, 0, 17 }, |
| 126 | |
| 127 | Package(){0x0016FFFF, 0, 0, 18 }, |
| 128 | Package(){0x0016FFFF, 1, 0, 17 }, |
| 129 | |
| 130 | /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ |
| 131 | Package(){0x0010FFFF, 0, 0, 0x12}, |
| 132 | Package(){0x0010FFFF, 1, 0, 0x11}, |
| 133 | |
| 134 | /* Bus 0, Dev 17 - SATA controller */ |
| 135 | Package(){0x0011FFFF, 0, 0, 19 }, |
| 136 | |
| 137 | /* Bus 0, Dev 21 PCIE Bridge */ |
| 138 | Package(){0x0015FFFF, 0, 0, 17 }, |
| 139 | Package(){0x0015FFFF, 1, 0, 18 }, |
| 140 | Package(){0x0015FFFF, 2, 0, 19 }, |
| 141 | Package(){0x0015FFFF, 3, 0, 16 }, |
| 142 | }) |
| 143 | |
| 144 | Name(PS2, Package(){ |
| 145 | /* The external GFX - Hooked to PCIe slot 2 */ |
| 146 | Package(){0x0000FFFF, 0, INTD, 0 }, |
| 147 | Package(){0x0000FFFF, 1, INTA, 0 }, |
| 148 | Package(){0x0000FFFF, 2, INTB, 0 }, |
| 149 | Package(){0x0000FFFF, 3, INTC, 0 }, |
| 150 | }) |
| 151 | Name(APS2, Package(){ |
| 152 | /* The external GFX - Hooked to PCIe slot 2 */ |
| 153 | Package(){0x0000FFFF, 0, 0, 18 }, |
| 154 | Package(){0x0000FFFF, 1, 0, 19 }, |
| 155 | Package(){0x0000FFFF, 2, 0, 16 }, |
| 156 | Package(){0x0000FFFF, 3, 0, 17 }, |
| 157 | }) |
| 158 | |
| 159 | /* black slot */ |
| 160 | Name(PS4, Package(){ |
| 161 | /* PCIe slot - Hooked to PCIe slot 4 */ |
| 162 | Package(){0x0000FFFF, 0, INTA, 0 }, |
| 163 | Package(){0x0000FFFF, 1, INTB, 0 }, |
| 164 | Package(){0x0000FFFF, 2, INTC, 0 }, |
| 165 | Package(){0x0000FFFF, 3, INTD, 0 }, |
| 166 | }) |
| 167 | Name(APS4, Package(){ |
| 168 | /* PCIe slot - Hooked to PCIe slot 4 */ |
| 169 | Package(){0x0000FFFF, 0, 0, 16 }, |
| 170 | Package(){0x0000FFFF, 1, 0, 17 }, |
| 171 | Package(){0x0000FFFF, 2, 0, 18 }, |
| 172 | Package(){0x0000FFFF, 3, 0, 19 }, |
| 173 | }) |
| 174 | |
| 175 | Name(PS5, Package(){ |
| 176 | /* PCIe slot - Hooked to PCIe slot 5 */ |
| 177 | Package(){0x0000FFFF, 0, INTB, 0 }, |
| 178 | Package(){0x0000FFFF, 1, INTC, 0 }, |
| 179 | Package(){0x0000FFFF, 2, INTD, 0 }, |
| 180 | Package(){0x0000FFFF, 3, INTA, 0 }, |
| 181 | }) |
| 182 | Name(APS5, Package(){ |
| 183 | /* PCIe slot - Hooked to PCIe slot 5 */ |
| 184 | Package(){0x0000FFFF, 0, 0, 17 }, |
| 185 | Package(){0x0000FFFF, 1, 0, 18 }, |
| 186 | Package(){0x0000FFFF, 2, 0, 19 }, |
| 187 | Package(){0x0000FFFF, 3, 0, 16 }, |
| 188 | }) |
| 189 | |
| 190 | Name(PS6, Package(){ |
| 191 | /* PCIe slot - Hooked to PCIe slot 6 */ |
| 192 | Package(){0x0000FFFF, 0, INTC, 0 }, |
| 193 | Package(){0x0000FFFF, 1, INTD, 0 }, |
| 194 | Package(){0x0000FFFF, 2, INTA, 0 }, |
| 195 | Package(){0x0000FFFF, 3, INTB, 0 }, |
| 196 | }) |
| 197 | Name(APS6, Package(){ |
| 198 | /* PCIe slot - Hooked to PCIe slot 6 */ |
| 199 | Package(){0x0000FFFF, 0, 0, 18 }, |
| 200 | Package(){0x0000FFFF, 1, 0, 19 }, |
| 201 | Package(){0x0000FFFF, 2, 0, 16 }, |
| 202 | Package(){0x0000FFFF, 3, 0, 17 }, |
| 203 | }) |
| 204 | |
| 205 | Name(PS7, Package(){ |
| 206 | /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ |
| 207 | Package(){0x0000FFFF, 0, INTD, 0 }, |
| 208 | Package(){0x0000FFFF, 1, INTA, 0 }, |
| 209 | Package(){0x0000FFFF, 2, INTB, 0 }, |
| 210 | Package(){0x0000FFFF, 3, INTC, 0 }, |
| 211 | }) |
| 212 | |
| 213 | Name(APS7, Package(){ |
| 214 | /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ |
| 215 | Package(){0x0000FFFF, 0, 0, 19 }, |
| 216 | Package(){0x0000FFFF, 1, 0, 16 }, |
| 217 | Package(){0x0000FFFF, 2, 0, 17 }, |
| 218 | Package(){0x0000FFFF, 3, 0, 18 }, |
| 219 | }) |
| 220 | |
| 221 | Name(PBR0, Package(){ |
| 222 | /* PCIx1 on SB */ |
| 223 | Package(){0x0000FFFF, 0, INTA, 0 }, |
| 224 | Package(){0x0000FFFF, 1, INTB, 0 }, |
| 225 | Package(){0x0000FFFF, 2, INTC, 0 }, |
| 226 | Package(){0x0000FFFF, 3, INTD, 0 }, |
| 227 | }) |
| 228 | Name(ABR0, Package(){ |
| 229 | /* PCIx1 on SB */ |
| 230 | Package(){0x0000FFFF, 0, 0, 0x10 }, |
| 231 | Package(){0x0000FFFF, 1, 0, 0x11 }, |
| 232 | Package(){0x0000FFFF, 2, 0, 0x12 }, |
| 233 | Package(){0x0000FFFF, 3, 0, 0x13 }, |
| 234 | }) |
| 235 | |
| 236 | Name(PBR1, Package(){ |
| 237 | /* Onboard network */ |
| 238 | Package(){0x0000FFFF, 0, INTB, 0 }, |
| 239 | Package(){0x0000FFFF, 1, INTC, 0 }, |
| 240 | Package(){0x0000FFFF, 2, INTD, 0 }, |
| 241 | Package(){0x0000FFFF, 3, INTA, 0 }, |
| 242 | }) |
| 243 | Name(ABR1, Package(){ |
| 244 | /* Onboard network */ |
| 245 | Package(){0x0000FFFF, 0, 0, 0x11 }, |
| 246 | Package(){0x0000FFFF, 1, 0, 0x12 }, |
| 247 | Package(){0x0000FFFF, 2, 0, 0x13 }, |
| 248 | Package(){0x0000FFFF, 3, 0, 0x10 }, |
| 249 | }) |
| 250 | |
| 251 | /* SB PCI Bridge */ |
| 252 | Name(PCIB, Package(){ |
| 253 | /* PCI slots: slot 0 behind Dev14, Fun4. */ |
| 254 | Package(){0x0005FFFF, 0, 0, 0x14 }, |
| 255 | Package(){0x0005FFFF, 1, 0, 0x15 }, |
| 256 | Package(){0x0005FFFF, 2, 0, 0x16 }, |
| 257 | Package(){0x0005FFFF, 3, 0, 0x17 }, |
| 258 | }) |