| Dave Frodin | c43bce5 | 2014-12-03 08:22:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Sage Electronic Engineering, LLC |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Dave Frodin | c43bce5 | 2014-12-03 08:22:46 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /* Memory related values */ |
| 17 | Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ |
| 18 | Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ |
| 19 | Name(PBLN, 0x0) /* Length of BIOS area */ |
| 20 | |
| 21 | Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ |
| 22 | Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ |
| 23 | Name(HPBA, 0xFED00000) /* Base address of HPET table */ |
| 24 | |
| 25 | Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ |
| 26 | |
| 27 | /* Some global data */ |
| 28 | Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ |
| 29 | Name(OSV, Ones) /* Assume nothing */ |
| 30 | Name(PMOD, One) /* Assume APIC */ |
| 31 | |
| 32 | /* AcpiGpe0Blk */ |
| 33 | OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) |
| 34 | Field(GP0B, ByteAcc, NoLock, Preserve) { |
| 35 | , 11, |
| 36 | USBS, 1, |
| 37 | } |