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Frank Vibrans69da1b62011-02-14 19:04:45 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Frank Vibrans69da1b62011-02-14 19:04:45 +000014 */
15
16/*
17DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
18 )
19 {
20 #include "routing.asl"
21 }
22*/
23
24/* Routing is in System Bus scope */
25Scope(\_SB) {
26 Name(PR0, Package(){
27 /* NB devices */
28 /* Bus 0, Dev 0 - RS780 Host Controller */
29 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Kerry Shehd6ed09b72011-12-22 12:18:37 +080030 Package(){0x0001FFFF, 0, INTC, 0 },
31 Package(){0x0001FFFF, 1, INTD, 0 },
Frank Vibrans69da1b62011-02-14 19:04:45 +000032 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
33 Package(){0x0002FFFF, 0, INTC, 0 },
34 Package(){0x0002FFFF, 1, INTD, 0 },
35 Package(){0x0002FFFF, 2, INTA, 0 },
36 Package(){0x0002FFFF, 3, INTB, 0 },
37 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
Kerry Shehd6ed09b72011-12-22 12:18:37 +080038 Package(){0x0003FFFF, 0, INTD, 0 },
39 Package(){0x0003FFFF, 1, INTA, 0 },
40 Package(){0x0003FFFF, 2, INTB, 0 },
41 Package(){0x0003FFFF, 3, INTC, 0 },
Frank Vibrans69da1b62011-02-14 19:04:45 +000042 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
43 Package(){0x0004FFFF, 0, INTA, 0 },
44 Package(){0x0004FFFF, 1, INTB, 0 },
45 Package(){0x0004FFFF, 2, INTC, 0 },
46 Package(){0x0004FFFF, 3, INTD, 0 },
47 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
Kerry Shehd6ed09b72011-12-22 12:18:37 +080048 Package(){0x0005FFFF, 0, INTB, 0 },
49 Package(){0x0005FFFF, 1, INTC, 0 },
50 Package(){0x0005FFFF, 2, INTD, 0 },
51 Package(){0x0005FFFF, 3, INTA, 0 },
Frank Vibrans69da1b62011-02-14 19:04:45 +000052 /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
53 Package(){0x0006FFFF, 0, INTC, 0 },
54 Package(){0x0006FFFF, 1, INTD, 0 },
55 Package(){0x0006FFFF, 2, INTA, 0 },
56 Package(){0x0006FFFF, 3, INTB, 0 },
57 /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
58 Package(){0x0007FFFF, 0, INTD, 0 },
59 Package(){0x0007FFFF, 1, INTA, 0 },
60 Package(){0x0007FFFF, 2, INTB, 0 },
61 Package(){0x0007FFFF, 3, INTC, 0 },
62
63 Package(){0x0009FFFF, 0, INTB, 0 },
64 Package(){0x0009FFFF, 1, INTC, 0 },
65 Package(){0x0009FFFF, 2, INTD, 0 },
66 Package(){0x0009FFFF, 3, INTA, 0 },
67
68 Package(){0x000AFFFF, 0, INTC, 0 },
69 Package(){0x000AFFFF, 1, INTD, 0 },
70 Package(){0x000AFFFF, 2, INTA, 0 },
71 Package(){0x000AFFFF, 3, INTB, 0 },
72
73 Package(){0x000BFFFF, 0, INTD, 0 },
74 Package(){0x000BFFFF, 1, INTA, 0 },
75 Package(){0x000BFFFF, 2, INTB, 0 },
76 Package(){0x000BFFFF, 3, INTC, 0 },
77
78 Package(){0x000CFFFF, 0, INTA, 0 },
79 Package(){0x000CFFFF, 1, INTB, 0 },
80 Package(){0x000CFFFF, 2, INTC, 0 },
81 Package(){0x000CFFFF, 3, INTD, 0 },
82
83 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
84
85 /* SB devices */
86 /* Bus 0, Dev 17 - SATA controller #2 */
87 /* Bus 0, Dev 18 - SATA controller #1 */
88 Package(){0x0011FFFF, 0, INTD, 0 },
89
90 /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
91 * EHCI, dev 18, 19 func 2 */
92 Package(){0x0012FFFF, 0, INTC, 0 },
93 Package(){0x0012FFFF, 1, INTB, 0 },
94
95 Package(){0x0013FFFF, 0, INTC, 0 },
96 Package(){0x0013FFFF, 1, INTB, 0 },
97
98 Package(){0x0016FFFF, 0, INTC, 0 },
99 Package(){0x0016FFFF, 1, INTB, 0 },
100
101 /* Package(){0x0014FFFF, 1, INTA, 0 }, */
102
103 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
104 Package(){0x0014FFFF, 0, INTA, 0 },
105 Package(){0x0014FFFF, 1, INTB, 0 },
106 Package(){0x0014FFFF, 2, INTC, 0 },
107 Package(){0x0014FFFF, 3, INTD, 0 },
108
109 Package(){0x0015FFFF, 0, INTA, 0 },
110 Package(){0x0015FFFF, 1, INTB, 0 },
111 Package(){0x0015FFFF, 2, INTC, 0 },
112 Package(){0x0015FFFF, 3, INTD, 0 },
113 })
114
115 Name(APR0, Package(){
116 /* NB devices in APIC mode */
117 /* Bus 0, Dev 0 - RS780 Host Controller */
118
119 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
120 Package(){0x0001FFFF, 0, 0, 18 },
Paul Menzela390d772013-06-22 13:47:06 +0200121 Package(){0x0001FFFF, 1, 0, 19 },
Frank Vibrans69da1b62011-02-14 19:04:45 +0000122
123 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
124 Package(){0x0002FFFF, 0, 0, 18 },
125 /* Package(){0x0002FFFF, 1, 0, 19 }, */
126 /* Package(){0x0002FFFF, 2, 0, 16 }, */
127 /* Package(){0x0002FFFF, 3, 0, 17 }, */
128
129 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
130 Package(){0x0003FFFF, 0, 0, 19 },
Kerry Shehd6ed09b72011-12-22 12:18:37 +0800131 Package(){0x0003FFFF, 1, 0, 16 },
132 Package(){0x0003FFFF, 2, 0, 17 },
133 Package(){0x0003FFFF, 3, 0, 18 },
Frank Vibrans69da1b62011-02-14 19:04:45 +0000134
135 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
136 Package(){0x0004FFFF, 0, 0, 16 },
Kerry Shehd6ed09b72011-12-22 12:18:37 +0800137 Package(){0x0004FFFF, 1, 0, 17 },
138 Package(){0x0004FFFF, 2, 0, 18 },
139 Package(){0x0004FFFF, 3, 0, 19 },
Frank Vibrans69da1b62011-02-14 19:04:45 +0000140
141 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
Kerry Shehd6ed09b72011-12-22 12:18:37 +0800142 Package(){0x0005FFFF, 0, 0, 17 },
143 Package(){0x0005FFFF, 1, 0, 18 },
144 Package(){0x0005FFFF, 2, 0, 19 },
145 Package(){0x0005FFFF, 3, 0, 16 },
Frank Vibrans69da1b62011-02-14 19:04:45 +0000146
147 /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
Kerry Shehd6ed09b72011-12-22 12:18:37 +0800148 Package(){0x0006FFFF, 0, 0, 18 },
149 Package(){0x0006FFFF, 1, 0, 19 },
150 Package(){0x0006FFFF, 2, 0, 16 },
151 Package(){0x0006FFFF, 3, 0, 17 },
Frank Vibrans69da1b62011-02-14 19:04:45 +0000152
153 /* Bus 0, Dev 7 - PCIe Bridge for network card */
Kerry Shehd6ed09b72011-12-22 12:18:37 +0800154 Package(){0x0007FFFF, 0, 0, 19 },
155 Package(){0x0007FFFF, 1, 0, 16 },
156 Package(){0x0007FFFF, 2, 0, 17 },
157 Package(){0x0007FFFF, 3, 0, 18 },
Frank Vibrans69da1b62011-02-14 19:04:45 +0000158
159 /* Bus 0, Dev 9 - PCIe Bridge for network card */
160 Package(){0x0009FFFF, 0, 0, 17 },
Kerry Shehd6ed09b72011-12-22 12:18:37 +0800161 Package(){0x0009FFFF, 1, 0, 16 },
162 Package(){0x0009FFFF, 2, 0, 17 },
163 Package(){0x0009FFFF, 3, 0, 18 },
Frank Vibrans69da1b62011-02-14 19:04:45 +0000164 /* Bus 0, Dev A - PCIe Bridge for network card */
165 Package(){0x000AFFFF, 0, 0, 18 },
Kerry Shehd6ed09b72011-12-22 12:18:37 +0800166 Package(){0x000AFFFF, 1, 0, 16 },
167 Package(){0x000AFFFF, 2, 0, 17 },
168 Package(){0x000AFFFF, 3, 0, 18 },
Frank Vibrans69da1b62011-02-14 19:04:45 +0000169 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
170
171 /* SB devices in APIC mode */
172 /* Bus 0, Dev 17 - SATA controller #2 */
173 /* Bus 0, Dev 18 - SATA controller #1 */
174 Package(){0x0011FFFF, 0, 0, 19 },
175
176 /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
177 * EHCI, dev 18, 19 func 2 */
178 Package(){0x0012FFFF, 0, 0, 18 },
179 Package(){0x0012FFFF, 1, 0, 17 },
180 /* Package(){0x0012FFFF, 2, 0, 18 }, */
181
182 Package(){0x0013FFFF, 0, 0, 18 },
183 Package(){0x0013FFFF, 1, 0, 17 },
184 /* Package(){0x0013FFFF, 2, 0, 16 }, */
185
186 /* Package(){0x00140000, 0, 0, 16 }, */
187
188 Package(){0x0016FFFF, 0, 0, 18 },
189 Package(){0x0016FFFF, 1, 0, 17 },
190
191 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
192 Package(){0x0014FFFF, 0, 0, 16 },
193 Package(){0x0014FFFF, 1, 0, 17 },
194 Package(){0x0014FFFF, 2, 0, 18 },
195 Package(){0x0014FFFF, 3, 0, 19 },
196 /* Package(){0x00140004, 2, 0, 18 }, */
197 /* Package(){0x00140004, 3, 0, 19 }, */
198 /* Package(){0x00140005, 1, 0, 17 }, */
199 /* Package(){0x00140006, 1, 0, 17 }, */
200
201 /* TODO: pcie */
202 Package(){0x0015FFFF, 0, 0, 16 },
203 Package(){0x0015FFFF, 1, 0, 17 },
204 Package(){0x0015FFFF, 2, 0, 18 },
205 Package(){0x0015FFFF, 3, 0, 19 },
206 })
207
208 Name(PR1, Package(){
209 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
210 Package(){0x0005FFFF, 0, INTA, 0 },
211 Package(){0x0005FFFF, 1, INTB, 0 },
212 Package(){0x0005FFFF, 2, INTC, 0 },
213 Package(){0x0005FFFF, 3, INTD, 0 },
214 })
215 Name(APR1, Package(){
216 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
217 Package(){0x0005FFFF, 0, 0, 18 },
218 Package(){0x0005FFFF, 1, 0, 19 },
219 /* Package(){0x0005FFFF, 2, 0, 20 }, */
220 /* Package(){0x0005FFFF, 3, 0, 17 }, */
221 })
222
223 Name(PS2, Package(){
224 /* The external GFX - Hooked to PCIe slot 2 */
225 Package(){0x0000FFFF, 0, INTC, 0 },
226 Package(){0x0000FFFF, 1, INTD, 0 },
227 Package(){0x0000FFFF, 2, INTA, 0 },
228 Package(){0x0000FFFF, 3, INTB, 0 },
229 })
230 Name(APS2, Package(){
231 /* The external GFX - Hooked to PCIe slot 2 */
232 Package(){0x0000FFFF, 0, 0, 18 },
233 Package(){0x0000FFFF, 1, 0, 19 },
234 Package(){0x0000FFFF, 2, 0, 16 },
235 Package(){0x0000FFFF, 3, 0, 17 },
236 })
237
238 Name(PS4, Package(){
239 /* PCIe slot - Hooked to PCIe slot 4 */
240 Package(){0x0000FFFF, 0, INTA, 0 },
241 Package(){0x0000FFFF, 1, INTB, 0 },
242 Package(){0x0000FFFF, 2, INTC, 0 },
243 Package(){0x0000FFFF, 3, INTD, 0 },
244 })
245 Name(APS4, Package(){
246 /* PCIe slot - Hooked to PCIe slot 4 */
247 Package(){0x0000FFFF, 0, 0, 16 },
248 Package(){0x0000FFFF, 1, 0, 17 },
249 Package(){0x0000FFFF, 2, 0, 18 },
250 Package(){0x0000FFFF, 3, 0, 19 },
251 })
252
253 Name(PS5, Package(){
254 /* PCIe slot - Hooked to PCIe slot 5 */
255 Package(){0x0000FFFF, 0, INTB, 0 },
256 Package(){0x0000FFFF, 1, INTC, 0 },
257 Package(){0x0000FFFF, 2, INTD, 0 },
258 Package(){0x0000FFFF, 3, INTA, 0 },
259 })
260 Name(APS5, Package(){
261 /* PCIe slot - Hooked to PCIe slot 5 */
262 Package(){0x0000FFFF, 0, 0, 17 },
263 Package(){0x0000FFFF, 1, 0, 18 },
264 Package(){0x0000FFFF, 2, 0, 19 },
265 Package(){0x0000FFFF, 3, 0, 16 },
266 })
267
268 Name(PS6, Package(){
269 /* PCIe slot - Hooked to PCIe slot 6 */
270 Package(){0x0000FFFF, 0, INTC, 0 },
271 Package(){0x0000FFFF, 1, INTD, 0 },
272 Package(){0x0000FFFF, 2, INTA, 0 },
273 Package(){0x0000FFFF, 3, INTB, 0 },
274 })
275 Name(APS6, Package(){
276 /* PCIe slot - Hooked to PCIe slot 6 */
277 Package(){0x0000FFFF, 0, 0, 18 },
278 Package(){0x0000FFFF, 1, 0, 19 },
279 Package(){0x0000FFFF, 2, 0, 16 },
280 Package(){0x0000FFFF, 3, 0, 17 },
281 })
282
283 Name(PS7, Package(){
284 /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
285 Package(){0x0000FFFF, 0, INTD, 0 },
286 Package(){0x0000FFFF, 1, INTA, 0 },
287 Package(){0x0000FFFF, 2, INTB, 0 },
288 Package(){0x0000FFFF, 3, INTC, 0 },
289 })
290 Name(APS7, Package(){
291 /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
292 Package(){0x0000FFFF, 0, 0, 19 },
293 Package(){0x0000FFFF, 1, 0, 16 },
294 Package(){0x0000FFFF, 2, 0, 17 },
295 Package(){0x0000FFFF, 3, 0, 18 },
296 })
297
298 Name(PS9, Package(){
299 /* PCIe slot - Hooked to PCIe slot 9 */
300 Package(){0x0000FFFF, 0, INTD, 0 },
301 Package(){0x0000FFFF, 1, INTA, 0 },
302 Package(){0x0000FFFF, 2, INTB, 0 },
303 Package(){0x0000FFFF, 3, INTC, 0 },
304 })
305 Name(APS9, Package(){
306 /* PCIe slot - Hooked to PCIe slot 9 */
307 Package(){0x0000FFFF, 0, 0, 17 },
308 Package(){0x0000FFFF, 1, 0, 18 },
309 Package(){0x0000FFFF, 2, 0, 19 },
310 Package(){0x0000FFFF, 3, 0, 16 },
311 })
312
313 Name(PSa, Package(){
314 /* PCIe slot - Hooked to PCIe slot 10 */
315 Package(){0x0000FFFF, 0, INTD, 0 },
316 Package(){0x0000FFFF, 1, INTA, 0 },
317 Package(){0x0000FFFF, 2, INTB, 0 },
318 Package(){0x0000FFFF, 3, INTC, 0 },
319 })
320 Name(APSa, Package(){
321 /* PCIe slot - Hooked to PCIe slot 10 */
322 Package(){0x0000FFFF, 0, 0, 18 },
323 Package(){0x0000FFFF, 1, 0, 19 },
324 Package(){0x0000FFFF, 2, 0, 16 },
325 Package(){0x0000FFFF, 3, 0, 17 },
326 })
327
328 Name(PE0, Package(){
329 /* PCIe slot - Hooked to PCIe slot 10 */
330 Package(){0x0000FFFF, 0, INTA, 0 },
331 Package(){0x0000FFFF, 1, INTB, 0 },
332 Package(){0x0000FFFF, 2, INTC, 0 },
333 Package(){0x0000FFFF, 3, INTD, 0 },
334 })
335 Name(APE0, Package(){
336 /* PCIe slot - Hooked to PCIe */
337 Package(){0x0000FFFF, 0, 0, 16 },
338 Package(){0x0000FFFF, 1, 0, 17 },
339 Package(){0x0000FFFF, 2, 0, 18 },
340 Package(){0x0000FFFF, 3, 0, 19 },
341 })
342
343 Name(PE1, Package(){
344 /* PCIe slot - Hooked to PCIe slot 10 */
345 Package(){0x0000FFFF, 0, INTB, 0 },
346 Package(){0x0000FFFF, 1, INTC, 0 },
347 Package(){0x0000FFFF, 2, INTD, 0 },
348 Package(){0x0000FFFF, 3, INTA, 0 },
349 })
350 Name(APE1, Package(){
351 /* PCIe slot - Hooked to PCIe */
352 Package(){0x0000FFFF, 0, 0, 17 },
353 Package(){0x0000FFFF, 1, 0, 18 },
354 Package(){0x0000FFFF, 2, 0, 19 },
355 Package(){0x0000FFFF, 3, 0, 16 },
356 })
357
358 Name(PE2, Package(){
359 /* PCIe slot - Hooked to PCIe slot 10 */
360 Package(){0x0000FFFF, 0, INTC, 0 },
361 Package(){0x0000FFFF, 1, INTD, 0 },
362 Package(){0x0000FFFF, 2, INTA, 0 },
363 Package(){0x0000FFFF, 3, INTB, 0 },
364 })
365 Name(APE2, Package(){
366 /* PCIe slot - Hooked to PCIe */
367 Package(){0x0000FFFF, 0, 0, 18 },
368 Package(){0x0000FFFF, 1, 0, 19 },
369 Package(){0x0000FFFF, 2, 0, 16 },
370 Package(){0x0000FFFF, 3, 0, 17 },
371 })
372
373 Name(PE3, Package(){
374 /* PCIe slot - Hooked to PCIe slot 10 */
375 Package(){0x0000FFFF, 0, INTD, 0 },
376 Package(){0x0000FFFF, 1, INTA, 0 },
377 Package(){0x0000FFFF, 2, INTB, 0 },
378 Package(){0x0000FFFF, 3, INTC, 0 },
379 })
380 Name(APE3, Package(){
381 /* PCIe slot - Hooked to PCIe */
382 Package(){0x0000FFFF, 0, 0, 19 },
383 Package(){0x0000FFFF, 1, 0, 16 },
384 Package(){0x0000FFFF, 2, 0, 17 },
385 Package(){0x0000FFFF, 3, 0, 18 },
386 })
387
388 Name(PCIB, Package(){
389 /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
390 Package(){0x0005FFFF, 0, 0, 0x14 },
391 Package(){0x0005FFFF, 1, 0, 0x15 },
392 Package(){0x0005FFFF, 2, 0, 0x16 },
393 Package(){0x0005FFFF, 3, 0, 0x17 },
394 Package(){0x0006FFFF, 0, 0, 0x15 },
395 Package(){0x0006FFFF, 1, 0, 0x16 },
396 Package(){0x0006FFFF, 2, 0, 0x17 },
397 Package(){0x0006FFFF, 3, 0, 0x14 },
398 Package(){0x0007FFFF, 0, 0, 0x16 },
399 Package(){0x0007FFFF, 1, 0, 0x17 },
400 Package(){0x0007FFFF, 2, 0, 0x14 },
401 Package(){0x0007FFFF, 3, 0, 0x15 },
402 })
403}