Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <stdlib.h> |
| 23 | #include <console/console.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <arch/romcc_io.h> |
| 26 | #include <device/pci_def.h> |
Duncan Laurie | f4d3623 | 2012-06-23 16:37:45 -0700 | [diff] [blame] | 27 | #include <elog.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 28 | #include "sandybridge.h" |
| 29 | #include "pcie_config.c" |
| 30 | |
| 31 | static void sandybridge_setup_bars(void) |
| 32 | { |
| 33 | /* Setting up Southbridge. In the northbridge code. */ |
| 34 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
| 35 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); |
| 36 | |
| 37 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 38 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ |
| 39 | |
| 40 | printk(BIOS_DEBUG, " done.\n"); |
| 41 | |
| 42 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 43 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
| 44 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
| 45 | printk(BIOS_DEBUG, " done.\n"); |
| 46 | |
| 47 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 48 | /* Set up all hardcoded northbridge BARs */ |
| 49 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 50 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); |
| 51 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); |
| 52 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); |
| 53 | pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ |
| 54 | pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); |
| 55 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); |
| 56 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32); |
| 57 | |
| 58 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 59 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 60 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 61 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 62 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 63 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 64 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 65 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 66 | |
Duncan Laurie | f4d3623 | 2012-06-23 16:37:45 -0700 | [diff] [blame] | 67 | #if CONFIG_ELOG_BOOT_COUNT |
| 68 | /* Increment Boot Counter for non-S3 resume */ |
| 69 | if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 70 | ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) |
| 71 | boot_count_increment(); |
| 72 | #endif |
| 73 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 74 | printk(BIOS_DEBUG, " done.\n"); |
Duncan Laurie | 9c4c6ab | 2012-06-29 15:38:02 -0700 | [diff] [blame] | 75 | |
| 76 | #if CONFIG_ELOG_BOOT_COUNT |
| 77 | /* Increment Boot Counter except when resuming from S3 */ |
| 78 | if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 79 | ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) |
| 80 | return; |
| 81 | boot_count_increment(); |
| 82 | #endif |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | static void sandybridge_setup_graphics(void) |
| 86 | { |
| 87 | u32 reg32; |
| 88 | u16 reg16; |
| 89 | u8 reg8; |
| 90 | |
| 91 | reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID); |
| 92 | switch (reg16) { |
| 93 | case 0x0102: /* GT1 Desktop */ |
| 94 | case 0x0106: /* GT1 Mobile */ |
| 95 | case 0x010a: /* GT1 Server */ |
| 96 | case 0x0112: /* GT2 Desktop */ |
| 97 | case 0x0116: /* GT2 Mobile */ |
| 98 | case 0x0122: /* GT2 Desktop >=1.3GHz */ |
| 99 | case 0x0126: /* GT2 Mobile >=1.3GHz */ |
Stefan Reinauer | 816e9d1 | 2013-01-14 10:25:43 -0800 | [diff] [blame] | 100 | case 0x0156: /* IvyBridge */ |
| 101 | case 0x0166: /* IvyBridge */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 102 | break; |
| 103 | default: |
| 104 | printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n"); |
| 105 | return; |
| 106 | } |
| 107 | |
| 108 | printk(BIOS_DEBUG, "Initializing Graphics...\n"); |
| 109 | |
| 110 | /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ |
| 111 | reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC); |
| 112 | reg16 &= ~0x00f8; |
| 113 | reg16 |= 1 << 3; |
| 114 | /* Program GTT memory by setting GGC[9:8] = 2MB */ |
| 115 | reg16 &= ~0x0300; |
| 116 | reg16 |= 2 << 8; |
| 117 | /* Enable VGA decode */ |
| 118 | reg16 &= ~0x0002; |
| 119 | pci_write_config16(PCI_DEV(0,0,0), GGC, reg16); |
| 120 | |
| 121 | /* Enable 256MB aperture */ |
| 122 | reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); |
| 123 | reg8 &= ~0x06; |
| 124 | reg8 |= 0x02; |
| 125 | pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); |
| 126 | |
| 127 | /* Erratum workarounds */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 128 | reg32 = MCHBAR32(0x5f00); |
| 129 | reg32 |= (1 << 9)|(1 << 10); |
| 130 | MCHBAR32(0x5f00) = reg32; |
| 131 | |
| 132 | /* Enable SA Clock Gating */ |
| 133 | reg32 = MCHBAR32(0x5f00); |
| 134 | MCHBAR32(0x5f00) = reg32 | 1; |
| 135 | |
| 136 | /* GPU RC6 workaround for sighting 366252 */ |
| 137 | reg32 = MCHBAR32(0x5d14); |
| 138 | reg32 |= (1 << 31); |
| 139 | MCHBAR32(0x5d14) = reg32; |
| 140 | |
| 141 | /* VLW */ |
| 142 | reg32 = MCHBAR32(0x6120); |
| 143 | reg32 &= ~(1 << 0); |
| 144 | MCHBAR32(0x6120) = reg32; |
| 145 | |
| 146 | reg32 = MCHBAR32(0x5418); |
| 147 | reg32 |= (1 << 4) | (1 << 5); |
| 148 | MCHBAR32(0x5418) = reg32; |
| 149 | } |
| 150 | |
| 151 | void sandybridge_early_initialization(int chipset_type) |
| 152 | { |
| 153 | u32 capid0_a; |
| 154 | u8 reg8; |
| 155 | |
| 156 | /* Device ID Override Enable should be done very early */ |
| 157 | capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); |
| 158 | if (capid0_a & (1 << 10)) { |
| 159 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); |
| 160 | reg8 &= ~7; /* Clear 2:0 */ |
| 161 | |
| 162 | if (chipset_type == SANDYBRIDGE_MOBILE) |
| 163 | reg8 |= 1; /* Set bit 0 */ |
| 164 | |
| 165 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); |
| 166 | } |
| 167 | |
| 168 | /* Setup all BARs required for early PCIe and raminit */ |
| 169 | sandybridge_setup_bars(); |
| 170 | |
| 171 | /* Device Enable */ |
| 172 | pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_HOST | DEVEN_IGD); |
| 173 | |
| 174 | sandybridge_setup_graphics(); |
| 175 | } |