Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __NORTHBRIDGE_INTEL_I945_I945_H__ |
| 21 | #define __NORTHBRIDGE_INTEL_I945_I945_H__ 1 |
| 22 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 23 | /* Northbridge BARs */ |
| 24 | #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ |
| 25 | #define DEFAULT_X60BAR 0xfed13000 |
| 26 | #define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ |
| 27 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
| 28 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
| 29 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 30 | #include "../../../southbridge/intel/i82801gx/i82801gx.h" |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 31 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 32 | /* Everything below this line is ignored in the DSDT */ |
| 33 | #ifndef __ACPI__ |
| 34 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 35 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
| 36 | |
| 37 | #define EPBAR 0x40 |
| 38 | #define MCHBAR 0x44 |
| 39 | #define PCIEXBAR 0x48 |
| 40 | #define DMIBAR 0x4c |
| 41 | #define X60BAR 0x60 |
| 42 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 43 | #define GGC 0x52 /* GMCH Graphics Control */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 44 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 45 | #define DEVEN 0x54 /* Device Enable */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 46 | #define DEVEN_D0F0 (1 << 0) |
| 47 | #define DEVEN_D1F0 (1 << 1) |
| 48 | #define DEVEN_D2F0 (1 << 3) |
| 49 | #define DEVEN_D2F1 (1 << 4) |
| 50 | #ifndef BOARD_DEVEN |
| 51 | #define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) |
| 52 | #endif |
| 53 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 54 | #define PAM0 0x90 |
| 55 | #define PAM1 0x91 |
| 56 | #define PAM2 0x92 |
| 57 | #define PAM3 0x93 |
| 58 | #define PAM4 0x94 |
| 59 | #define PAM5 0x95 |
| 60 | #define PAM6 0x96 |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 61 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 62 | #define LAC 0x97 /* Legacy Access Control */ |
| 63 | #define TOLUD 0x9c /* Top of Low Used Memory */ |
| 64 | #define SMRAM 0x9d /* System Management RAM Control */ |
| 65 | #define ESMRAM 0x9e /* Extended System Management RAM Control */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 66 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 67 | #define TOM 0xa0 |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 68 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 69 | #define SKPAD 0xdc /* Scratchpad Data */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 70 | |
| 71 | /* Device 0:1.0 PCI configuration space (PCI Express) */ |
| 72 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 73 | #define BCTRL1 0x3e /* 16bit */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 74 | |
| 75 | |
| 76 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 77 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 78 | #define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 79 | |
| 80 | |
| 81 | /* |
| 82 | * MCHBAR |
| 83 | */ |
| 84 | |
| 85 | #define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) |
| 86 | #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) |
| 87 | #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) |
| 88 | |
| 89 | /* Chipset Control Registers */ |
| 90 | #define FSBPMC3 0x40 /* 32bit */ |
| 91 | #define FSBPMC4 0x44 /* 32bit */ |
| 92 | #define FSBSNPCTL 0x48 /* 32bit */ |
| 93 | #define SLPCTL 0x90 /* 32bit */ |
| 94 | |
| 95 | #define C0DRB0 0x100 /* 8bit */ |
| 96 | #define C0DRB1 0x101 /* 8bit */ |
| 97 | #define C0DRB2 0x102 /* 8bit */ |
| 98 | #define C0DRB3 0x103 /* 8bit */ |
| 99 | #define C0DRA0 0x108 /* 8bit */ |
| 100 | #define C0DRA2 0x109 /* 8bit */ |
| 101 | #define C0DCLKDIS 0x10c /* 8bit */ |
| 102 | #define C0BNKARC 0x10e /* 16bit */ |
| 103 | #define C0DRT0 0x110 /* 32bit */ |
| 104 | #define C0DRT1 0x114 /* 32bit */ |
| 105 | #define C0DRT2 0x118 /* 32bit */ |
| 106 | #define C0DRT3 0x11c /* 32bit */ |
| 107 | #define C0DRC0 0x120 /* 32bit */ |
| 108 | #define C0DRC1 0x124 /* 32bit */ |
| 109 | #define C0DRC2 0x128 /* 32bit */ |
| 110 | #define C0AIT 0x130 /* 64bit */ |
| 111 | #define C0DCCFT 0x138 /* 64bit */ |
| 112 | #define C0GTEW 0x140 /* 32bit */ |
| 113 | #define C0GTC 0x144 /* 32bit */ |
| 114 | #define C0DTPEW 0x148 /* 64bit */ |
| 115 | #define C0DTAEW 0x150 /* 64bit */ |
| 116 | #define C0DTC 0x158 /* 32bit */ |
| 117 | #define C0DMC 0x164 /* 32bit */ |
| 118 | #define C0ODT 0x168 /* 64bit */ |
| 119 | |
| 120 | #define C1DRB0 0x180 /* 8bit */ |
| 121 | #define C1DRB1 0x181 /* 8bit */ |
| 122 | #define C1DRB2 0x182 /* 8bit */ |
| 123 | #define C1DRB3 0x183 /* 8bit */ |
| 124 | #define C1DRA0 0x188 /* 8bit */ |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 125 | #define C1DRA2 0x189 /* 8bit */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 126 | #define C1DCLKDIS 0x18c /* 8bit */ |
| 127 | #define C1BNKARC 0x18e /* 16bit */ |
| 128 | #define C1DRT0 0x190 /* 32bit */ |
| 129 | #define C1DRT1 0x194 /* 32bit */ |
| 130 | #define C1DRT2 0x198 /* 32bit */ |
| 131 | #define C1DRT3 0x19c /* 32bit */ |
| 132 | #define C1DRC0 0x1a0 /* 32bit */ |
| 133 | #define C1DRC1 0x1a4 /* 32bit */ |
| 134 | #define C1DRC2 0x1a8 /* 32bit */ |
| 135 | #define C1AIT 0x1b0 /* 64bit */ |
| 136 | #define C1DCCFT 0x1b8 /* 64bit */ |
| 137 | #define C1GTEW 0x1c0 /* 32bit */ |
| 138 | #define C1GTC 0x1c4 /* 32bit */ |
| 139 | #define C1DTPEW 0x1c8 /* 64bit */ |
| 140 | #define C1DTAEW 0x1d0 /* 64bit */ |
| 141 | #define C1DTC 0x1d8 /* 32bit */ |
| 142 | #define C1DMC 0x1e4 /* 32bit */ |
| 143 | #define C1ODT 0x1e8 /* 64bit */ |
| 144 | |
| 145 | #define DCC 0x200 /* 32bit */ |
| 146 | #define CCCFT 0x208 /* 64bit */ |
| 147 | #define WCC 0x218 /* 32bit */ |
| 148 | #define MMARB0 0x220 /* 32bit */ |
| 149 | #define MMARB1 0x224 /* 32bit */ |
| 150 | #define SBTEST 0x230 /* 32bit */ |
| 151 | #define SBOCC 0x238 /* 32bit */ |
| 152 | #define ODTC 0x284 /* 32bit */ |
| 153 | #define SMVREFC 0x2a0 /* 32bit */ |
| 154 | #define DRTST 0x2a8 /* 32bit */ |
| 155 | #define REPC 0x2e0 /* 32bit */ |
| 156 | #define DQSMT 0x2f4 /* 16bit */ |
| 157 | #define RCVENMT 0x2f8 /* 32bit */ |
| 158 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 159 | #define C0R0B00DQST 0x300 /* 64bit */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 160 | |
| 161 | #define C0WL0REOST 0x340 /* 8bit */ |
| 162 | #define C0WL1REOST 0x341 /* 8bit */ |
| 163 | #define C0WL2REOST 0x342 /* 8bit */ |
| 164 | #define C0WL3REOST 0x343 /* 8bit */ |
| 165 | #define WDLLBYPMODE 0x360 /* 16bit */ |
| 166 | #define C0WDLLCMC 0x36c /* 32bit */ |
| 167 | #define C0HCTC 0x37c /* 8bit */ |
| 168 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 169 | #define C1R0B00DQST 0x380 /* 64bit */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 170 | |
| 171 | #define C1WL0REOST 0x3c0 /* 8bit */ |
| 172 | #define C1WL1REOST 0x3c1 /* 8bit */ |
| 173 | #define C1WL2REOST 0x3c2 /* 8bit */ |
| 174 | #define C1WL3REOST 0x3c3 /* 8bit */ |
| 175 | #define C1WDLLCMC 0x3ec /* 32bit */ |
| 176 | #define C1HCTC 0x3fc /* 8bit */ |
| 177 | |
| 178 | #define GBRCOMPCTL 0x400 /* 32bit */ |
| 179 | |
| 180 | #define SMSRCTL 0x408 /* XXX who knows */ |
| 181 | #define C0DRAMW 0x40c /* 16bit */ |
| 182 | #define G1SC 0x410 /* 8bit */ |
| 183 | #define G2SC 0x418 /* 8bit */ |
| 184 | #define G3SC 0x420 /* 8bit */ |
| 185 | #define G4SC 0x428 /* 8bit */ |
| 186 | #define G5SC 0x430 /* 8bit */ |
| 187 | #define G6SC 0x438 /* 8bit */ |
| 188 | |
| 189 | #define C1DRAMW 0x48c /* 16bit */ |
| 190 | #define G7SC 0x490 /* 8bit */ |
| 191 | #define G8SC 0x498 /* 8bit */ |
| 192 | |
| 193 | #define G1SRPUT 0x500 /* 256bit */ |
| 194 | #define G1SRPDT 0x520 /* 256bit */ |
| 195 | #define G2SRPUT 0x540 /* 256bit */ |
| 196 | #define G2SRPDT 0x560 /* 256bit */ |
| 197 | #define G3SRPUT 0x580 /* 256bit */ |
| 198 | #define G3SRPDT 0x5a0 /* 256bit */ |
| 199 | #define G4SRPUT 0x5c0 /* 256bit */ |
| 200 | #define G4SRPDT 0x5e0 /* 256bit */ |
| 201 | #define G5SRPUT 0x600 /* 256bit */ |
| 202 | #define G5SRPDT 0x620 /* 256bit */ |
| 203 | #define G6SRPUT 0x640 /* 256bit */ |
| 204 | #define G6SRPDT 0x660 /* 256bit */ |
| 205 | #define G7SRPUT 0x680 /* 256bit */ |
| 206 | #define G7SRPDT 0x6a0 /* 256bit */ |
| 207 | #define G8SRPUT 0x6c0 /* 256bit */ |
| 208 | #define G8SRPDT 0x6e0 /* 256bit */ |
| 209 | |
| 210 | /* Clock Controls */ |
| 211 | #define CLKCFG 0xc00 /* 32bit */ |
| 212 | #define UPMC1 0xc14 /* 16bit */ |
| 213 | #define CPCTL 0xc16 /* 16bit */ |
| 214 | #define SSKPD 0xc1c /* 16bit (scratchpad) */ |
| 215 | #define UPMC2 0xc20 /* 16bit */ |
| 216 | #define UPMC4 0xc30 /* 32bit */ |
| 217 | #define PLLMON 0xc34 /* 32bit */ |
| 218 | #define HGIPMC2 0xc38 /* 32bit */ |
| 219 | |
| 220 | /* Thermal Management Controls */ |
| 221 | #define TSC1 0xc88 /* 8bit */ |
| 222 | #define TSS1 0xc8a /* 8bit */ |
| 223 | #define TR1 0xc8b /* 8bit */ |
| 224 | #define TSTTP1 0xc8c /* 32bit */ |
| 225 | #define TCO1 0xc92 /* 8bit */ |
| 226 | #define THERM1_1 0xc94 /* 8bit */ |
| 227 | #define TCOF1 0xc96 /* 8bit */ |
| 228 | #define TIS1 0xc9a /* 16bit */ |
| 229 | #define TSTTP1_2 0xc9c /* 32bit */ |
| 230 | #define IUB 0xcd0 /* 32bit */ |
| 231 | #define TSC0_1 0xcd8 /* 8bit */ |
| 232 | #define TSS0 0xcda /* 8bit */ |
| 233 | #define TR0 0xcdb /* 8bit */ |
| 234 | #define TSTTP0_1 0xcdc /* 32bit */ |
| 235 | #define TCO0 0xce2 /* 8bit */ |
| 236 | #define THERM0_1 0xce4 /* 8bit */ |
| 237 | #define TCOF0 0xce6 /* 8bit */ |
| 238 | #define TIS0 0xcea /* 16bit */ |
| 239 | #define TSTTP0_2 0xcec /* 32bit */ |
| 240 | #define TERRCMD 0xcf0 /* 8bit */ |
| 241 | #define TSMICMD 0xcf1 /* 8bit */ |
| 242 | #define TSCICMD 0xcf2 /* 8bit */ |
| 243 | #define TINTRCMD 0xcf3 /* 8bit */ |
| 244 | #define EXTTSCS 0xcff /* 8bit */ |
| 245 | #define DFT_STRAP1 0xe08 /* 32bit */ |
| 246 | |
| 247 | /* ACPI Power Management Controls */ |
| 248 | |
| 249 | #define MIPMC3 0xbd8 /* 32bit */ |
| 250 | |
| 251 | #define C2C3TT 0xf00 /* 32bit */ |
| 252 | #define C3C4TT 0xf04 /* 32bit */ |
| 253 | |
| 254 | #define MIPMC4 0xf08 /* 16bit */ |
| 255 | #define MIPMC5 0xf0a /* 16bit */ |
| 256 | #define MIPMC6 0xf0c /* 16bit */ |
| 257 | #define MIPMC7 0xf0e /* 16bit */ |
| 258 | #define PMCFG 0xf10 /* 32bit */ |
| 259 | #define SLFRCS 0xf14 /* 32bit */ |
| 260 | #define GIPMC1 0xfb0 /* 32bit */ |
| 261 | #define FSBPMC1 0xfb8 /* 32bit */ |
| 262 | #define UPMC3 0xfc0 /* 32bit */ |
| 263 | #define ECO 0xffc /* 32bit */ |
| 264 | |
| 265 | /* |
| 266 | * EPBAR - Egress Port Root Complex Register Block |
| 267 | */ |
| 268 | |
| 269 | #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) |
| 270 | #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) |
| 271 | #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) |
| 272 | |
| 273 | #define EPPVCCAP1 0x004 /* 32bit */ |
| 274 | #define EPPVCCAP2 0x008 /* 32bit */ |
| 275 | |
| 276 | #define EPVC0RCAP 0x010 /* 32bit */ |
| 277 | #define EPVC0RCTL 0x014 /* 32bit */ |
| 278 | #define EPVC0RSTS 0x01a /* 16bit */ |
| 279 | |
| 280 | #define EPVC1RCAP 0x01c /* 32bit */ |
| 281 | #define EPVC1RCTL 0x020 /* 32bit */ |
| 282 | #define EPVC1RSTS 0x026 /* 16bit */ |
| 283 | |
| 284 | #define EPVC1MTS 0x028 /* 32bit */ |
| 285 | #define EPVC1IST 0x038 /* 64bit */ |
| 286 | |
| 287 | #define EPESD 0x044 /* 32bit */ |
| 288 | |
| 289 | #define EPLE1D 0x050 /* 32bit */ |
| 290 | #define EPLE1A 0x058 /* 64bit */ |
| 291 | #define EPLE2D 0x060 /* 32bit */ |
| 292 | #define EPLE2A 0x068 /* 64bit */ |
| 293 | |
| 294 | #define PORTARB 0x100 /* 256bit */ |
| 295 | |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 296 | /* |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 297 | * DMIBAR |
| 298 | */ |
| 299 | |
| 300 | #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) |
| 301 | #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) |
| 302 | #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) |
| 303 | |
| 304 | #define DMIVCECH 0x000 /* 32bit */ |
| 305 | #define DMIPVCCAP1 0x004 /* 32bit */ |
| 306 | #define DMIPVCCAP2 0x008 /* 32bit */ |
| 307 | |
| 308 | #define DMIPVCCCTL 0x00c /* 16bit */ |
| 309 | |
| 310 | #define DMIVC0RCAP 0x010 /* 32bit */ |
| 311 | #define DMIVC0RCTL0 0x014 /* 32bit */ |
| 312 | #define DMIVC0RSTS 0x01a /* 16bit */ |
| 313 | |
| 314 | #define DMIVC1RCAP 0x01c /* 32bit */ |
| 315 | #define DMIVC1RCTL 0x020 /* 32bit */ |
| 316 | #define DMIVC1RSTS 0x026 /* 16bit */ |
| 317 | |
| 318 | #define DMILE1D 0x050 /* 32bit */ |
| 319 | #define DMILE1A 0x058 /* 64bit */ |
| 320 | #define DMILE2D 0x060 /* 32bit */ |
| 321 | #define DMILE2A 0x068 /* 64bit */ |
| 322 | |
| 323 | #define DMILCAP 0x084 /* 32bit */ |
| 324 | #define DMILCTL 0x088 /* 16bit */ |
| 325 | #define DMILSTS 0x08a /* 16bit */ |
| 326 | |
| 327 | #define DMICTL1 0x0f0 /* 32bit */ |
| 328 | #define DMICTL2 0x0fc /* 32bit */ |
| 329 | |
| 330 | #define DMICC 0x208 /* 32bit */ |
| 331 | |
| 332 | #define DMIDRCCFG 0xeb4 /* 32bit */ |
| 333 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 334 | static inline void barrier(void) { asm("" ::: "memory"); } |
| 335 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 336 | int i945_silicon_revision(void); |
| 337 | void i945_early_initialization(void); |
| 338 | void i945_late_initialization(void); |
| 339 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 340 | /* provided by mainboard code */ |
| 341 | void setup_ich7_gpios(void); |
| 342 | |
| 343 | /* debugging functions */ |
| 344 | void print_pci_devices(void); |
| 345 | void dump_pci_device(unsigned dev); |
| 346 | void dump_pci_devices(void); |
| 347 | void dump_spd_registers(void); |
| 348 | void dump_mem(unsigned start, unsigned end); |
| 349 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 350 | #endif |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 351 | #endif |