blob: 3803230d55761bacc5c652e8231a11ffff6613f1 [file] [log] [blame]
Felix Held3f3eca92020-01-23 17:12:32 +01001/* SPDX-License-Identifier: GPL-2.0-or-later */
Fabian Kunkelf75c3b42015-05-25 17:04:28 +02002
Fabian Kunkelf75c3b42015-05-25 17:04:28 +02003#include <device/device.h>
4#include <device/pnp.h>
5#include <superio/conf_mode.h>
Fabian Kunkelf75c3b42015-05-25 17:04:28 +02006#include <pc80/keyboard.h>
Elyes HAOUAS2329a252019-05-15 22:11:18 +02007
Fabian Kunkelf75c3b42015-05-25 17:04:28 +02008#include "f81866d.h"
9#include "fintek_internal.h"
10
11static void f81866d_init(struct device *dev)
12{
13 if (!dev->enabled)
14 return;
15
16 switch (dev->path.pnp.device) {
17 /* TODO: Might potentially need extra code for serial, wdt etc. */
18 case F81866D_KBC:
Timothy Pearson448e3862015-11-24 14:12:01 -060019 pc_keyboard_init(NO_AUX_DEVICE);
Fabian Kunkelf75c3b42015-05-25 17:04:28 +020020 break;
21 case F81866D_HWM:
22 // Fixing temp sensor read out and init Fan control
23 f81866d_hwm_init(dev);
24 break;
Fabian Kunkel145796e2016-07-07 15:15:18 +020025 case F81866D_SP1:
26 // Enable Uart1 and IRQ share register
27 f81866d_uart_init(dev);
28 break;
29 case F81866D_SP2:
30 // Enable Uart2 and IRQ share register
31 f81866d_uart_init(dev);
32 break;
33 case F81866D_SP3:
34 // Enable Uart3 and IRQ share register
35 f81866d_uart_init(dev);
36 break;
37 case F81866D_SP4:
38 // Enable Uart4 and IRQ share register
39 f81866d_uart_init(dev);
40 break;
Fabian Kunkelf75c3b42015-05-25 17:04:28 +020041 }
42}
43
44static struct device_operations ops = {
45 .read_resources = pnp_read_resources,
46 .set_resources = pnp_set_resources,
47 .enable_resources = pnp_enable_resources,
48 .enable = pnp_alt_enable,
49 .init = f81866d_init,
50 .ops_pnp_mode = &pnp_conf_mode_8787_aa,
51};
52
53static struct pnp_info pnp_dev_info[] = {
54 /* TODO: Some of the 0x7f8 etc. values may not be correct. */
Felix Held8ac8ac62018-07-06 21:43:34 +020055 { NULL, F81866D_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
56 { NULL, F81866D_SP1, PNP_IO0 | PNP_IRQ0, 0x7f8, },
57 { NULL, F81866D_SP2, PNP_IO0 | PNP_IRQ0, 0x7f8, },
58 { NULL, F81866D_SP3, PNP_IO0 | PNP_IRQ0, 0x7f8, },
59 { NULL, F81866D_SP4, PNP_IO0 | PNP_IRQ0, 0x7f8, },
60 { NULL, F81866D_SP5, PNP_IO0 | PNP_IRQ0, 0x7f8, },
61 { NULL, F81866D_SP6, PNP_IO0 | PNP_IRQ0, 0x7f8, },
62 { NULL, F81866D_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
63 { NULL, F81866D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
64 { NULL, F81866D_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, },
65 { NULL, F81866D_GPIO, PNP_IRQ0, },
66 { NULL, F81866D_PME, },
67 { NULL, F81866D_WDT, },
Fabian Kunkelf75c3b42015-05-25 17:04:28 +020068};
69
70static void enable_dev(struct device *dev)
71{
72 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
73}
74
75struct chip_operations superio_fintek_f81866d_ops = {
76 CHIP_NAME("Fintek F81866AD-I Super I/O")
77 .enable_dev = enable_dev
78};