blob: eabe87380a269f4555c171ad3ef789b8fc5ceed6 [file] [log] [blame]
Patrick Georgi11f00792020-03-04 15:10:45 +01001/* SPDX-License-Identifier: GPL-2.0-only */
Aaron Durbin956c4f22015-09-05 13:31:14 -05002
Kyösti Mälkkied318f22019-01-11 21:07:36 +02003/* CACHE_ROM_SIZE defined here. */
4#include <cpu/x86/mtrr.h>
5
Aaron Durbin956c4f22015-09-05 13:31:14 -05006/* This file is included inside a SECTIONS block */
7. = CONFIG_DCACHE_RAM_BASE;
8.car.data . (NOLOAD) : {
Andrey Petrovdd56de92016-02-25 17:22:17 -08009 _car_region_start = . ;
Julius Wernercd49cce2019-03-05 16:53:33 -080010#if CONFIG(PAGING_IN_CACHE_AS_RAM)
Aaron Durbin0f35af82018-04-18 01:00:27 -060011 /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
12 * aligned when using this option. */
13 _pagetables = . ;
14 . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
15 _epagetables = . ;
16#endif
Joel Kitchingd6f71d02019-02-21 12:37:55 +080017 /* Vboot work buffer only needs to be available when verified boot
18 * starts in bootblock. */
Julius Wernercd49cce2019-03-05 16:53:33 -080019#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
Joel Kitching0097f552019-02-21 12:36:55 +080020 VBOOT2_WORK(., 12K)
Aaron Durbin75c51d92015-09-29 16:31:20 -050021#endif
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +010022 /* Vboot measured boot TCPA log measurements.
23 * Needs to be transferred until CBMEM is available
24 */
Bill XIEc79e96b2019-08-22 20:28:36 +080025#if CONFIG(TPM_MEASURED_BOOT)
26 TPM_TCPA_LOG(., 2K)
Arthur Heymans3c613042019-04-21 23:59:47 +020027#endif
Andrey Petrovee9e4ae2016-02-08 17:17:05 -080028 /* Stack for CAR stages. Since it persists across all stages that
29 * use CAR it can be reused. The chipset/SoC is expected to provide
30 * the stack size. */
Arthur Heymansdf9cdcf2019-11-09 06:50:20 +010031 _car_stack = .;
Andrey Petrovee9e4ae2016-02-08 17:17:05 -080032 . += CONFIG_DCACHE_BSP_STACK_SIZE;
Arthur Heymansdf9cdcf2019-11-09 06:50:20 +010033 _ecar_stack = .;
Aaron Durbindd6fa932015-09-24 12:18:07 -050034 /* The pre-ram cbmem console as well as the timestamp region are fixed
Arthur Heymans4cc9b6c2018-12-28 17:53:36 +010035 * in size. Therefore place them above the car global section so that
36 * multiple stages (romstage and verstage) have a consistent
37 * link address of these shared objects. */
Kyösti Mälkki513a1a82018-06-03 12:29:50 +030038 PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
Julius Wernercd49cce2019-03-05 16:53:33 -080039#if CONFIG(PAGING_IN_CACHE_AS_RAM)
Aaron Durbin0f35af82018-04-18 01:00:27 -060040 . = ALIGN(32);
41 /* Page directory pointer table resides here. There are 4 8-byte entries
42 * totalling 32 bytes that need to be 32-byte aligned. The reason the
43 * pdpt are not colocated with the rest of the page tables is to reduce
44 * fragmentation of the CAR space that persists across stages. */
45 _pdpt = .;
46 . += 32;
47 _epdpt = .;
48#endif
Kyösti Mälkki3dd23a52019-08-22 15:06:50 +030049
Furquan Shaikh549080b2018-05-17 23:30:28 -070050 TIMESTAMP(., 0x200)
Julius Werner7fc92862019-11-18 13:01:06 -080051
52#if !CONFIG(NO_FMAP_CACHE)
Julius Wernercefe89e2019-11-06 19:29:44 -080053 FMAP_CACHE(., FMAP_SIZE)
Julius Werner7fc92862019-11-18 13:01:06 -080054#endif
Kyösti Mälkki3dd23a52019-08-22 15:06:50 +030055
Arthur Heymansdf9cdcf2019-11-09 06:50:20 +010056 _car_ehci_dbg_info = .;
Kyösti Mälkkif88208e2019-01-31 08:29:32 +020057 /* Reserve sizeof(struct ehci_dbg_info). */
Kyösti Mälkki45ad4f02019-01-31 19:24:04 +020058 . += 80;
Arthur Heymansdf9cdcf2019-11-09 06:50:20 +010059 _ecar_ehci_dbg_info = .;
Kyösti Mälkki3dd23a52019-08-22 15:06:50 +030060
Kyösti Mälkki910490f2019-08-22 12:56:22 +030061 /* _bss and _ebss provide symbols to per-stage
Aaron Durbindd6fa932015-09-24 12:18:07 -050062 * variables that are not shared like the timestamp and the pre-ram
63 * cbmem console. This is useful for clearing this area on a per-stage
Arthur Heymansfdb8b132019-11-28 14:00:01 +010064 * basis when more than one stage uses cache-as-ram. */
Kyösti Mälkki910490f2019-08-22 12:56:22 +030065
66 . = ALIGN(ARCH_POINTER_ALIGN_SIZE);
67 _bss = .;
Kyösti Mälkkia165c072019-08-22 09:44:44 +030068 /* Allow global uninitialized variables for stages without CAR teardown. */
Aaron Durbin76ab2b72018-10-30 12:15:10 -060069 *(.bss)
70 *(.bss.*)
71 *(.sbss)
72 *(.sbss.*)
Aaron Durbin956c4f22015-09-05 13:31:14 -050073 . = ALIGN(ARCH_POINTER_ALIGN_SIZE);
Kyösti Mälkki910490f2019-08-22 12:56:22 +030074 _ebss = .;
Andrey Petrovdd56de92016-02-25 17:22:17 -080075
Harshit Sharmaa6ebe082020-07-20 00:21:05 -070076#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)
77 _shadow_size = (_ebss - _car_region_start) >> 3;
78 REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE)
79#endif
80 _car_unallocated_start = .;
Andrey Petrovdd56de92016-02-25 17:22:17 -080081 _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
Aaron Durbin956c4f22015-09-05 13:31:14 -050082}
Kyösti Mälkkied318f22019-01-11 21:07:36 +020083. = _car_region_end;
84.car.mrc_var . (NOLOAD) : {
85 . += CONFIG_DCACHE_RAM_MRC_VAR_SIZE;
86}
87
88#if ENV_BOOTBLOCK
89_car_mtrr_end = .;
90_car_mtrr_start = _car_region_start;
91
92_car_mtrr_size = _car_mtrr_end - _car_mtrr_start;
93_car_mtrr_sz_log2 = 1 << LOG2CEIL(_car_mtrr_size);
94_car_mtrr_mask = ~(MAX(4096, _car_mtrr_sz_log2) - 1);
95
96#if !CONFIG(NO_XIP_EARLY_STAGES)
97_xip_program_sz_log2 = 1 << LOG2CEIL(_ebootblock - _bootblock);
98_xip_mtrr_mask = ~(MAX(4096, _xip_program_sz_log2) - 1);
99#endif
100
101_rom_mtrr_mask = ~(CACHE_ROM_SIZE - 1);
102_rom_mtrr_base = _rom_mtrr_mask;
103#endif
Aaron Durbin956c4f22015-09-05 13:31:14 -0500104
105/* Global variables are not allowed in romstage
106 * This section is checked during stage creation to ensure
107 * that there are no global variables present
108 */
109
110. = 0xffffff00;
111.illegal_globals . : {
Nico Huber98fc4262016-01-23 01:24:33 +0100112 *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
113 *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
Aaron Durbin956c4f22015-09-05 13:31:14 -0500114}
115
Aaron Durbindd6fa932015-09-24 12:18:07 -0500116_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
Julius Wernercd49cce2019-03-05 16:53:33 -0800117#if CONFIG(PAGING_IN_CACHE_AS_RAM)
Aaron Durbin0f35af82018-04-18 01:00:27 -0600118_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
119#endif
Patrick Rudolphd72d52a2018-11-12 19:26:54 +0100120_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");