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Patrick Georgi11f00792020-03-04 15:10:45 +01001## SPDX-License-Identifier: GPL-2.0-only
Stefan Reinauer425b61e2015-03-15 04:29:35 +01002
Stefan Reinauera48ca842015-04-04 01:58:28 +02003config ARCH_X86
4 bool
Stefan Reinauera48ca842015-04-04 01:58:28 +02005 select PCI
Kyösti Mälkkiec151f02018-06-03 22:48:51 +03006 select RELOCATABLE_MODULES
Harshit Sharma65bec1c2020-08-05 22:25:27 -07007 select HAVE_ASAN_IN_RAMSTAGE
Stefan Reinauera48ca842015-04-04 01:58:28 +02008
Stefan Reinauer68671202015-03-15 04:34:03 +01009# stage selectors for x86
10
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070011config ARCH_BOOTBLOCK_X86_32
Gabe Black5fbfc912013-07-07 13:52:37 -070012 bool
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070013 select ARCH_X86
14
Stefan Reinauer77b16552015-01-14 19:51:47 +010015config ARCH_VERSTAGE_X86_32
16 bool
Arthur Heymansb86e96a2019-02-10 17:00:56 +010017 select ARCH_X86
Stefan Reinauer77b16552015-01-14 19:51:47 +010018
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070019config ARCH_ROMSTAGE_X86_32
20 bool
Arthur Heymansb86e96a2019-02-10 17:00:56 +010021 select ARCH_X86
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070022
Patrick Georgi29eeece2018-10-31 14:24:47 +010023config ARCH_POSTCAR_X86_32
24 bool
25 default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE
26
Furquan Shaikh99ac98f2014-04-23 10:18:48 -070027config ARCH_RAMSTAGE_X86_32
28 bool
Arthur Heymansb86e96a2019-02-10 17:00:56 +010029 select ARCH_X86
Gabe Black5fbfc912013-07-07 13:52:37 -070030
Stefan Reinauer68671202015-03-15 04:34:03 +010031# stage selectors for x64
32
33config ARCH_BOOTBLOCK_X86_64
34 bool
Stefan Reinauer68671202015-03-15 04:34:03 +010035 select ARCH_X86
36
37config ARCH_VERSTAGE_X86_64
38 bool
Arthur Heymansb86e96a2019-02-10 17:00:56 +010039 select ARCH_X86
Stefan Reinauer68671202015-03-15 04:34:03 +010040
41config ARCH_ROMSTAGE_X86_64
42 bool
Arthur Heymansb86e96a2019-02-10 17:00:56 +010043 select ARCH_X86
Stefan Reinauer68671202015-03-15 04:34:03 +010044
Patrick Georgi29eeece2018-10-31 14:24:47 +010045config ARCH_POSTCAR_X86_64
46 bool
47 default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE
48
Stefan Reinauer68671202015-03-15 04:34:03 +010049config ARCH_RAMSTAGE_X86_64
50 bool
Arthur Heymansb86e96a2019-02-10 17:00:56 +010051 select ARCH_X86
52
53if ARCH_X86
Stefan Reinauer68671202015-03-15 04:34:03 +010054
Patrick Rudolphb1ef7252019-09-28 17:44:01 +020055config ARCH_X86_64_PGTBL_LOC
56 hex "x86_64 page table location in CBFS"
57 depends on ARCH_BOOTBLOCK_X86_64
58 default 0xfffea000
59 help
60 The position where to place pagetables. Needs to be known at
61 compile time. Must not overlap other files in CBFS.
62
Martin Roth0cd9ff82016-02-01 17:33:37 -070063config USE_MARCH_586
64 def_bool n
65 help
66 Allow a platform or processor to select to be compiled using
67 the '-march=i586' option instead of the typical '-march=i686'
68
Uwe Hermann168b11b2009-10-07 16:15:40 +000069# This is an SMP option. It relates to starting up APs.
70# It is usually set in mainboard/*/Kconfig.
71# TODO: Improve description.
Sven Schnelle51676b12012-07-29 19:18:03 +020072config AP_IN_SIPI_WAIT
73 bool
74 default n
Stefan Reinauer2a6f3902012-10-15 13:38:09 -070075 depends on ARCH_X86 && SMP
Ronald G. Minnich6ed39d92009-08-29 02:59:35 +000076
Marshall Dawson67910db2019-11-01 17:30:05 -060077config X86_RESET_VECTOR
78 hex
79 depends on ARCH_X86
80 default 0xfffffff0
81 help
82 Specify the location of the x86 reset vector. In traditional devices
83 this must match the architectural reset vector to produce a bootable
84 image. Nontraditional designs may use this to position the reset
85 vector into its desired location.
86
Martin Roth8418fd42019-04-22 16:26:23 -060087config RESET_VECTOR_IN_RAM
88 bool
89 depends on ARCH_X86
Felix Heldca928c62020-04-04 01:47:37 +020090 select NO_XIP_EARLY_STAGES
Martin Roth8418fd42019-04-22 16:26:23 -060091 help
Felix Heldca928c62020-04-04 01:47:37 +020092 Select this option if the x86 processor's reset vector is in
93 preinitialized DRAM instead of the traditional 0xfffffff0 location.
Martin Roth8418fd42019-04-22 16:26:23 -060094
Kyösti Mälkkif8c7c232012-04-06 04:03:50 +030095# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
96# can boot AP CPUs to enable their shared caches.
97config SIPI_VECTOR_IN_ROM
98 bool
99 default n
100 depends on ARCH_X86
101
Ronald G. Minnich83bd46e2018-09-16 09:59:54 -0700102# Set the rambase for systems that still need it, only 5 chipsets as of
103# Sep 2018. This value was 0x100000, chosen to match the entry point
104# of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense
105# for as long as we need it; with luck, that won't be much longer.
106# In the long term, both RAMBASE and RAMTOP should be removed.
107# This value leaves more than 1 MiB which is required for fam10
108# and broadwell_de.
Patrick Georgi0588d192009-08-12 15:00:51 +0000109config RAMBASE
110 hex
Ronald G. Minnich83bd46e2018-09-16 09:59:54 -0700111 default 0xe00000
Patrick Georgi0588d192009-08-12 15:00:51 +0000112
Kyösti Mälkkibec853e2016-06-15 02:25:00 +0300113config RAMTOP
114 hex
Ronald G. Minnich83bd46e2018-09-16 09:59:54 -0700115 default 0x1000000
Kyösti Mälkkibec853e2016-06-15 02:25:00 +0300116 depends on ARCH_X86
117
Alexandru Gagniuc6a622312015-10-27 10:27:30 -0700118# Traditionally BIOS region on SPI flash boot media was memory mapped right below
119# 4G and it was the last region in the IFD. This way translation between CPU
120# address space to flash address was trivial. However some IFDs on newer SoCs
121# have BIOS region sandwiched between descriptor and other regions. Turning off
122# this option enables soc code to provide custom mmap_boot.c which can be used to
123# implement complex translation.
124config X86_TOP4G_BOOTMEDIA_MAP
125 bool
126 default y
127
Ronald G. Minnichb5e777c2013-07-22 20:17:18 +0200128# This is something you almost certainly don't want to mess with.
129# How many SIPIs do we send when starting up APs and cores?
130# The answer in 2000 or so was '2'. Nowadays, on many systems,
131# it is 1. Set a safe default here, and you can override it
132# on reasonable platforms.
133config NUM_IPI_STARTS
134 int
135 default 2
136
Naresh G Solanki04bb4802016-12-13 21:16:46 +0530137config PRERAM_CBMEM_CONSOLE_SIZE
138 hex
139 default 0xc00
140 help
141 Increase this value if preram cbmem console is getting truncated
142
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000143config PC80_SYSTEM
144 bool
Furquan Shaikh99ac98f2014-04-23 10:18:48 -0700145 default y if ARCH_X86
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000146
Lee Leahyfdc8c8b2016-06-07 08:45:17 -0700147config BOOTBLOCK_DEBUG_SPINLOOP
148 bool
149 default n
150 help
151 Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
152 for a JTAG debugger to break into the execution sequence.
153
Patrick Georgia865b172011-01-14 07:40:24 +0000154config HAVE_CMOS_DEFAULT
155 def_bool n
Martin Rothf76303e2016-11-16 15:45:22 -0700156 depends on HAVE_OPTION_TABLE
Patrick Georgia865b172011-01-14 07:40:24 +0000157
158config CMOS_DEFAULT_FILE
159 string
Patrick Georgib8fba862020-06-17 21:06:53 +0200160 default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
Patrick Georgia865b172011-01-14 07:40:24 +0000161 depends on HAVE_CMOS_DEFAULT
162
Patrick Georgid4d5e4d2012-03-16 19:28:15 +0100163config IOAPIC_INTERRUPTS_ON_FSB
164 bool
165 default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
166
167config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
168 bool
169 default n
170
Kyösti Mälkkib433d262018-05-24 09:56:11 +0300171config HPET_ADDRESS_OVERRIDE
172 def_bool n
173
Patrick Georgi9aeb6942012-10-05 21:54:38 +0200174config HPET_ADDRESS
175 hex
176 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
177
Stefan Reinauer84833442012-11-13 15:04:12 -0800178config ID_SECTION_OFFSET
179 hex
180 default 0x80
Patrick Georgic32a52c2015-06-22 21:10:34 +0200181
Arthur Heymansc05b1a62019-11-22 21:01:30 +0100182# 64KiB default bootblock size
Aaron Durbin65ac3d82016-02-11 14:36:19 -0600183config C_ENV_BOOTBLOCK_SIZE
184 hex
185 default 0x10000
Andrey Petrovccd300b2016-02-28 22:04:51 -0800186
187# Default address romstage is to be linked at
188config ROMSTAGE_ADDR
189 hex
190 default 0x2000000
191
192# Default address verstage is to be linked at
193config VERSTAGE_ADDR
194 hex
195 default 0x2000000
Aaron Durbin7f8afe02016-03-18 12:21:23 -0500196
197# Use the post CAR infrastructure for tearing down cache-as-ram
Elyes HAOUAS777ea892016-07-29 07:40:41 +0200198# from a program loaded in RAM and subsequently loading ramstage.
Aaron Durbin7f8afe02016-03-18 12:21:23 -0500199config POSTCAR_STAGE
Kyösti Mälkki0f5e01a2019-08-09 07:11:07 +0300200 def_bool y
201 depends on ARCH_X86
Felix Heldca928c62020-04-04 01:47:37 +0200202 depends on !RESET_VECTOR_IN_RAM
Lee Leahyd131ea32016-06-08 13:40:08 -0700203
204config VERSTAGE_DEBUG_SPINLOOP
205 bool
206 default n
207 help
208 Add a spin (JMP .) in assembly_entry.S during early verstage to wait
209 for a JTAG debugger to break into the execution sequence.
210
211config ROMSTAGE_DEBUG_SPINLOOP
212 bool
213 default n
214 help
215 Add a spin (JMP .) in assembly_entry.S during early romstage to wait
216 for a JTAG debugger to break into the execution sequence.
Martin Roth408fda72016-12-15 16:04:55 -0700217
218choice
219 prompt "Bootblock behaviour"
220 default BOOTBLOCK_SIMPLE
Kyösti Mälkkib8d575c2019-12-16 16:00:49 +0200221 depends on !VBOOT
Martin Roth408fda72016-12-15 16:04:55 -0700222
223config BOOTBLOCK_SIMPLE
224 bool "Always load fallback"
225
226config BOOTBLOCK_NORMAL
Arthur Heymans6f751542019-06-08 11:28:52 +0200227 select CONFIGURABLE_CBFS_PREFIX
Martin Roth408fda72016-12-15 16:04:55 -0700228 bool "Switch to normal if CMOS says so"
229
230endchoice
231
Martin Roth408fda72016-12-15 16:04:55 -0700232config SKIP_MAX_REBOOT_CNT_CLEAR
233 bool "Do not clear reboot count after successful boot"
234 depends on BOOTBLOCK_NORMAL
235 help
236 Do not clear the reboot count immediately after successful boot.
237 Set to allow the payload to control normal/fallback image recovery.
238 Note that it is the responsibility of the payload to reset the
Paul Menzelb9499022019-01-08 16:21:31 +0100239 normal boot bit to 1 after each successful boot.
Marc Jones7a2d4ea2017-08-25 18:54:23 -0600240
Furquan Shaikhbf4b7b02020-04-30 18:08:16 -0700241config ACPI_BERT
Nico Huber9df72e02018-11-24 18:25:50 +0100242 bool
Marc Jones7a2d4ea2017-08-25 18:54:23 -0600243 depends on HAVE_ACPI_TABLES
244 help
Furquan Shaikhbf4b7b02020-04-30 18:08:16 -0700245 Build an ACPI Boot Error Record Table.
Aaron Durbinf49ddb62018-01-24 17:35:58 -0700246
247config COLLECT_TIMESTAMPS_NO_TSC
248 bool
249 default n
250 depends on COLLECT_TIMESTAMPS
251 help
252 Use a non-TSC platform-dependent source for timestamps.
253
254config COLLECT_TIMESTAMPS_TSC
255 bool
256 default y if !COLLECT_TIMESTAMPS_NO_TSC
257 default n
258 depends on COLLECT_TIMESTAMPS
259 help
260 Use the TSC as the timestamp source.
Aaron Durbin0f35af82018-04-18 01:00:27 -0600261
262config PAGING_IN_CACHE_AS_RAM
263 bool
264 default n
265 depends on ARCH_X86
266 help
267 Chipsets scan select this option to preallocate area in cache-as-ram
268 for storing paging data structures. PAE paging is currently the
269 only thing being supported.
270
271config NUM_CAR_PAGE_TABLE_PAGES
272 int
273 default 5
274 depends on PAGING_IN_CACHE_AS_RAM
275 help
276 The number of 4KiB pages that should be pre-allocated for page tables.
Aaron Durbin4b032e42018-04-20 01:39:30 -0600277
278# Provide the interrupt handlers to every stage. Not all
279# stages may take advantage.
280config IDT_IN_EVERY_STAGE
281 bool
282 default n
283 depends on ARCH_X86
Nico Huber33fcaf92018-10-10 22:44:20 +0200284
285config HAVE_CF9_RESET
286 bool
287
288config HAVE_CF9_RESET_PREPARE
289 bool
290 depends on HAVE_CF9_RESET
Kyösti Mälkkib72b5d92019-07-04 21:08:17 +0300291
292config PIRQ_ROUTE
293 bool
294 default n
295
296config MAX_PIRQ_LINKS
297 int
298 default 4
299 depends on PIRQ_ROUTE
300 help
301 This variable specifies the number of PIRQ interrupt links which are
302 routable. On most chipsets, this is 4, INTA through INTD. Some
303 chipsets offer more than four links, commonly up to INTH. They may
304 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
305 table specifies links greater than 4, pirq_route_irqs will not
306 function properly, unless this variable is correctly set.
Arthur Heymansb86e96a2019-02-10 17:00:56 +0100307
Duncan Laurief02bf352020-03-17 18:32:54 -0700308config MAX_ACPI_TABLE_SIZE_KB
309 int
310 default 144
311 help
312 Set the maximum size of all ACPI tables in KiB.
313
Furquan Shaikh46514c22020-06-11 11:59:07 -0700314config MEMLAYOUT_LD_FILE
315 string
316 default "src/arch/x86/memlayout.ld"
317
Arthur Heymansb86e96a2019-02-10 17:00:56 +0100318endif