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Patrick Georgic49d7a32020-05-08 22:50:46 +02001## SPDX-License-Identifier: GPL-2.0-only
Patrick Georgi0588d192009-08-12 15:00:51 +00002
Uwe Hermannad8c95f2012-04-12 22:00:03 +02003mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +00004
Uwe Hermannc04be932009-10-05 13:55:28 +00005menu "General setup"
6
Lee Leahybb70c402017-04-03 07:38:20 -07007config COREBOOT_BUILD
8 bool
9 default y
10
Uwe Hermannc04be932009-10-05 13:55:28 +000011config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000012 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000013 help
14 Append an extra string to the end of the coreboot version.
15
Uwe Hermann168b11b2009-10-07 16:15:40 +000016 This can be useful if, for instance, you want to append the
17 respective board's hostname or some other identifying string to
18 the coreboot version number, so that you can easily distinguish
19 boot logs of different boards from each other.
20
Arthur Heymans6f751542019-06-08 11:28:52 +020021config CONFIGURABLE_CBFS_PREFIX
22 bool
23 help
24 Select this to prompt to use to configure the prefix for cbfs files.
25
Arthur Heymans6010eb22019-10-06 13:34:20 +020026choice
27 prompt "CBFS prefix to use"
28 depends on CONFIGURABLE_CBFS_PREFIX
29 default CBFS_PREFIX_FALLBACK
30
31config CBFS_PREFIX_FALLBACK
32 bool "fallback"
33
34config CBFS_PREFIX_NORMAL
35 bool "normal"
36
37config CBFS_PREFIX_DIY
38 bool "Define your own cbfs prefix"
39
40endchoice
41
Patrick Georgi4b8a2412010-02-09 19:35:16 +000042config CBFS_PREFIX
Arthur Heymans6010eb22019-10-06 13:34:20 +020043 string "CBFS prefix to use" if CBFS_PREFIX_DIY
44 default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
45 default "normal" if CBFS_PREFIX_NORMAL
Patrick Georgi4b8a2412010-02-09 19:35:16 +000046 help
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
49
Patrick Georgi23d89cc2010-03-16 01:17:19 +000050choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020051 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000052 default COMPILER_GCC
53 help
54 This option allows you to select the compiler used for building
55 coreboot.
Martin Rotha5a628e82016-01-19 12:01:09 -070056 You must build the coreboot crosscompiler for the board that you
57 have selected.
58
59 To build all the GCC crosscompilers (takes a LONG time), run:
60 make crossgcc
61
62 For help on individual architectures, run the command:
63 make help_toolchain
Patrick Georgi23d89cc2010-03-16 01:17:19 +000064
65config COMPILER_GCC
66 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020067 help
68 Use the GNU Compiler Collection (GCC) to build coreboot.
69
70 For details see http://gcc.gnu.org.
71
Patrick Georgi23d89cc2010-03-16 01:17:19 +000072config COMPILER_LLVM_CLANG
Martin Rotha5a628e82016-01-19 12:01:09 -070073 bool "LLVM/clang (TESTING ONLY - Not currently working)"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020074 help
Martin Rotha5a628e82016-01-19 12:01:09 -070075 Use LLVM/clang to build coreboot. To use this, you must build the
76 coreboot version of the clang compiler. Run the command
77 make clang
78 Note that this option is not currently working correctly and should
79 really only be selected if you're trying to work on getting clang
80 operational.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020081
82 For details see http://clang.llvm.org.
83
Patrick Georgi23d89cc2010-03-16 01:17:19 +000084endchoice
85
Patrick Georgi9b0de712013-12-29 18:45:23 +010086config ANY_TOOLCHAIN
87 bool "Allow building with any toolchain"
88 default n
Patrick Georgi9b0de712013-12-29 18:45:23 +010089 help
90 Many toolchains break when building coreboot since it uses quite
91 unusual linker features. Unless developers explicitely request it,
92 we'll have to assume that they use their distro compiler by mistake.
93 Make sure that using patched compilers is a conscious decision.
94
Patrick Georgi516a2a72010-03-25 21:45:25 +000095config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +020096 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +000097 default n
98 help
99 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200100
101 Requires the ccache utility in your system $PATH.
102
103 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +0000104
Sol Boucher69b88bf2015-02-26 11:47:19 -0800105config FMD_GENPARSER
106 bool "Generate flashmap descriptor parser using flex and bison"
107 default n
Sol Boucher69b88bf2015-02-26 11:47:19 -0800108 help
109 Enable this option if you are working on the flashmap descriptor
110 parser and made changes to fmd_scanner.l or fmd_parser.y.
111
112 Otherwise, say N to use the provided pregenerated scanner/parser.
113
Martin Rothf411b702017-04-09 19:12:42 -0600114config UTIL_GENPARSER
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100115 bool "Generate SCONFIG & BINCFG parser using flex and bison"
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000116 default n
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000117 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200118 Enable this option if you are working on the sconfig device tree
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100119 parser or bincfg and made changes to the .l or .y files.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200120
Sol Boucher69b88bf2015-02-26 11:47:19 -0800121 Otherwise, say N to use the provided pregenerated scanner/parser.
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000122
Joe Korty6d772522010-05-19 18:41:15 +0000123config USE_OPTION_TABLE
124 bool "Use CMOS for configuration values"
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000125 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000126 help
127 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200128 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000129
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600130config STATIC_OPTION_TABLE
131 bool "Load default configuration values into CMOS on each boot"
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600132 depends on USE_OPTION_TABLE
133 help
134 Enable this option to reset "CMOS" NVRAM values to default on
135 every boot. Use this if you want the NVRAM configuration to
136 never be modified from its default values.
137
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000138config COMPRESS_RAMSTAGE
139 bool "Compress ramstage with LZMA"
Subrata Banikb5962a92019-06-08 12:29:02 +0530140 depends on HAVE_RAMSTAGE
Martin Roth75e5cb72016-12-15 15:05:37 -0700141 # Default value set at the end of the file
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000142 help
Arthur Heymans7f229332019-11-08 11:59:25 +0100143 Compress ramstage to save memory in the flash image.
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000144
Julius Werner09f29212015-09-29 13:51:35 -0700145config COMPRESS_PRERAM_STAGES
146 bool "Compress romstage and verstage with LZ4"
Subrata Banikb5962a92019-06-08 12:29:02 +0530147 depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
Martin Roth75e5cb72016-12-15 15:05:37 -0700148 # Default value set at the end of the file
Julius Werner09f29212015-09-29 13:51:35 -0700149 help
150 Compress romstage and (if it exists) verstage with LZ4 to save flash
151 space and speed up boot, since the time for reading the image from SPI
152 (and in the vboot case verifying it) is usually much greater than the
153 time spent decompressing. Doesn't work for XIP stages (assume all
154 ARCH_X86 for now) for obvious reasons.
155
Julius Werner99f46832018-05-16 14:14:04 -0700156config COMPRESS_BOOTBLOCK
157 bool
Subrata Banikb5962a92019-06-08 12:29:02 +0530158 depends on HAVE_BOOTBLOCK
Julius Werner99f46832018-05-16 14:14:04 -0700159 help
160 This option can be used to compress the bootblock with LZ4 and attach
161 a small self-decompression stub to its front. This can drastically
162 reduce boot time on platforms where the bootblock is loaded over a
163 very slow connection and bootblock size trumps all other factors for
Jonathan Neuschäfer2930a722018-09-29 17:42:52 +0200164 speed. Since using this option usually requires changes to the
Julius Werner99f46832018-05-16 14:14:04 -0700165 SoC memlayout and possibly extra support code, it should not be
166 user-selectable. (There's no real point in offering this to the user
167 anyway... if it works and saves boot time, you would always want it.)
168
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200169config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200170 bool "Include the coreboot .config file into the ROM image"
Martin Roth75e5cb72016-12-15 15:05:37 -0700171 # Default value set at the end of the file
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200172 help
173 Include the .config file that was used to compile coreboot
174 in the (CBFS) ROM image. This is useful if you want to know which
175 options were used to build a specific coreboot.rom image.
176
Daniele Forsi53847a22014-07-22 18:00:56 +0200177 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200178
179 You can use the following command to easily list the options:
180
181 grep -a CONFIG_ coreboot.rom
182
183 Alternatively, you can also use cbfstool to print the image
184 contents (including the raw 'config' item we're looking for).
185
186 Example:
187
188 $ cbfstool coreboot.rom print
189 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
190 offset 0x0
191 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600192
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200193 Name Offset Type Size
Elyes HAOUAS2119d0b2020-02-16 10:01:33 +0100194 cmos_layout.bin 0x0 CMOS layout 1159
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200195 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200196 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200197 fallback/payload 0x80dc0 payload 51526
198 config 0x8d740 raw 3324
199 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200200
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700201config COLLECT_TIMESTAMPS
202 bool "Create a table of timestamps collected during boot"
Paul Menzel4e4a7632015-10-11 11:57:44 +0200203 default y if ARCH_X86
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700204 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200205 Make coreboot create a table of timer-ID/timer-value pairs to
206 allow measuring time spent at different phases of the boot process.
207
Martin Rothb22bbe22018-03-07 15:32:16 -0700208config TIMESTAMPS_ON_CONSOLE
209 bool "Print the timestamp values on the console"
210 default n
211 depends on COLLECT_TIMESTAMPS
212 help
Kyösti Mälkki8b93cb72020-01-09 08:41:46 +0200213 Print the timestamps to the debug console if enabled at level info.
Martin Rothb22bbe22018-03-07 15:32:16 -0700214
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200215config USE_BLOBS
216 bool "Allow use of binary-only repository"
Felix Helda6b887e2019-12-28 19:10:12 +0100217 default y
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200218 help
219 This draws in the blobs repository, which contains binary files that
220 might be required for some chipsets or boards.
221 This flag ensures that a "Free" option remains available for users.
222
Marshall Dawson20ce4002019-10-28 15:55:03 -0600223config USE_AMD_BLOBS
224 bool "Allow AMD blobs repository (with license agreement)"
225 depends on USE_BLOBS
226 help
227 This draws in the amd_blobs repository, which contains binary files
228 distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
229 etc. Selecting this item to download or clone the repo implies your
230 agreement to the AMD license agreement. A copy of the license text
231 may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
232 and your copy of the license is present in the repo once downloaded.
233
234 Note that for some products, omitting PSP, SMU images, or other items
235 may result in a nonbooting coreboot.rom.
236
Julius Wernerbc1cb382020-06-18 15:03:22 -0700237config USE_QC_BLOBS
Benjamin Doron999d29e2020-07-01 01:47:22 +0000238 bool "Allow QC blobs repository (selecting this agrees to the license!)"
Julius Wernerbc1cb382020-06-18 15:03:22 -0700239 depends on USE_BLOBS
240 help
241 This draws in the qc_blobs repository, which contains binary files
242 distributed by Qualcomm that are required to build firmware for
243 certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP
244 firmware). If you say Y here you are implicitly agreeing to the
245 Qualcomm license agreement which can be found at:
246 https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE
247
248 *****************************************************
249 PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN
250 ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION!
251 *****************************************************
252
253 Not selecting this option means certain Qualcomm SoCs and related
254 mainboards cannot be built and will be hidden from the "Mainboards"
255 section.
256
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800257config COVERAGE
258 bool "Code coverage support"
259 depends on COMPILER_GCC
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800260 help
261 Add code coverage support for coreboot. This will store code
262 coverage information in CBMEM for extraction from user space.
263 If unsure, say N.
264
Ryan Salsamendiab37e9a2017-06-11 21:07:31 -0700265config UBSAN
266 bool "Undefined behavior sanitizer support"
267 default n
268 help
269 Instrument the code with checks for undefined behavior. If unsure,
270 say N because it adds a small performance penalty and may abort
271 on code that happens to work in spite of the UB.
272
Harshit Sharma0b1ec5a2020-08-05 21:16:31 -0700273config HAVE_ASAN_IN_ROMSTAGE
274 bool
Harshit Sharma2bcaba02020-06-09 20:25:16 -0700275 default n
Harshit Sharma0b1ec5a2020-08-05 21:16:31 -0700276
277config ASAN_IN_ROMSTAGE
278 bool
279 default n
280 help
281 Enable address sanitizer in romstage for platform.
282
283config HAVE_ASAN_IN_RAMSTAGE
284 bool
285 default n
286
287config ASAN_IN_RAMSTAGE
288 bool
289 default n
290 help
291 Enable address sanitizer in ramstage for platform.
292
293config ASAN
294 bool "Address sanitizer support"
295 default n
296 select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE
297 select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE
Harshit Sharma2bcaba02020-06-09 20:25:16 -0700298 help
299 Enable address sanitizer - runtime memory debugger,
300 designed to find out-of-bounds accesses and use-after-scope bugs.
301
302 This feature consumes up to 1/8 of available memory and brings about
303 ~1.5x performance slowdown.
304
305 If unsure, say N.
306
Harshit Sharma0b1ec5a2020-08-05 21:16:31 -0700307if ASAN
Harshit Sharma3b9cc852020-07-06 23:38:31 -0700308 comment "Before using this feature, make sure that "
309 comment "asan_shadow_offset_callback patch is applied to GCC."
310endif
311
Kyösti Mälkki6766f4f2019-12-18 00:19:06 +0200312choice
313 prompt "Stage Cache for ACPI S3 resume"
Kyösti Mälkki18a8ba42020-07-02 21:48:38 +0300314 default NO_STAGE_CACHE if !HAVE_ACPI_RESUME
Kyösti Mälkki6766f4f2019-12-18 00:19:06 +0200315 default TSEG_STAGE_CACHE if SMM_TSEG
316
317config NO_STAGE_CACHE
318 bool "Disabled"
319 help
320 Do not save any component in stage cache for resume path. On resume,
321 all components would be read back from CBFS again.
322
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +0300323config TSEG_STAGE_CACHE
Kyösti Mälkki6766f4f2019-12-18 00:19:06 +0200324 bool "TSEG"
325 depends on SMM_TSEG
Stefan Reinauer58470e32014-10-17 13:08:36 +0200326 help
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +0300327 The option enables stage cache support for platform. Platform
328 can stash copies of postcar, ramstage and raw runtime data
329 inside SMM TSEG, to be restored on S3 resume path.
330
331config CBMEM_STAGE_CACHE
Kyösti Mälkki6766f4f2019-12-18 00:19:06 +0200332 bool "CBMEM"
333 depends on !SMM_TSEG
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +0300334 help
335 The option enables stage cache support for platform. Platform
336 can stash copies of postcar, ramstage and raw runtime data
337 inside CBMEM.
338
339 While the approach is faster than reloading stages from boot media
340 it is also a possible attack scenario via which OS can possibly
341 circumvent SMM locks and SPI write protections.
342
343 If unsure, select 'N'
Stefan Reinauer58470e32014-10-17 13:08:36 +0200344
Kyösti Mälkki6766f4f2019-12-18 00:19:06 +0200345endchoice
346
Stefan Reinauer58470e32014-10-17 13:08:36 +0200347config UPDATE_IMAGE
348 bool "Update existing coreboot.rom image"
Stefan Reinauer58470e32014-10-17 13:08:36 +0200349 help
350 If this option is enabled, no new coreboot.rom file
351 is created. Instead it is expected that there already
352 is a suitable file for further processing.
353 The bootblock will not be modified.
354
Martin Roth5942e062016-01-20 14:59:21 -0700355 If unsure, select 'N'
356
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400357config BOOTSPLASH_IMAGE
358 bool "Add a bootsplash image"
359 help
360 Select this option if you have a bootsplash image that you would
361 like to add to your ROM.
362
363 This will only add the image to the ROM. To actually run it check
364 options under 'Display' section.
365
366config BOOTSPLASH_FILE
367 string "Bootsplash path and filename"
368 depends on BOOTSPLASH_IMAGE
Martin Roth75e5cb72016-12-15 15:05:37 -0700369 # Default value set at the end of the file
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400370 help
371 The path and filename of the file to use as graphical bootsplash
372 screen. The file format has to be jpg.
373
Duncan Laurie36e6c6f2020-05-09 19:20:10 -0700374config FW_CONFIG
375 bool "Firmware Configuration Probing"
376 default n
377 help
378 Enable support for probing devices with fw_config. This is a simple
379 bitmask broken into fields and options for probing.
380
381config FW_CONFIG_SOURCE_CBFS
382 bool "Obtain Firmware Configuration value from CBFS"
383 depends on FW_CONFIG
384 default n
385 help
386 With this option enabled coreboot will look for the 32bit firmware
387 configuration value in CBFS at the selected prefix with the file name
388 "fw_config". This option will override other sources and allow the
389 local image to preempt the mainboard selected source.
390
391config FW_CONFIG_SOURCE_CHROMEEC_CBI
392 bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
393 depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
394 default n
395 help
396 This option tells coreboot to read the firmware configuration value
397 from the Google Chrome Embedded Controller CBI interface. This source
398 is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
399 found in CBFS.
400
Nico Huber94cdec62019-06-06 19:36:02 +0200401config HAVE_RAMPAYLOAD
402 bool
403
Subrata Banik7e893a02019-05-06 14:17:41 +0530404config RAMPAYLOAD
405 bool "Enable coreboot flow without executing ramstage"
Subrata Banik86dbe0f2019-06-28 18:18:37 +0530406 default y if ARCH_X86
Nico Huber94cdec62019-06-06 19:36:02 +0200407 depends on HAVE_RAMPAYLOAD
Subrata Banik7e893a02019-05-06 14:17:41 +0530408 help
409 If this option is enabled, coreboot flow will skip ramstage
410 loading and execution of ramstage to load payload.
411
412 Instead it is expected to load payload from postcar stage itself.
413
414 In this flow coreboot will perform basic x86 initialization
415 (DRAM resource allocation), MTRR programming,
416 Skip PCI enumeration logic and only allocate BAR for fixed devices
417 (bootable devices, TPM over GSPI).
418
Subrata Banik37bead62020-02-09 19:13:52 +0530419config HAVE_CONFIGURABLE_RAMSTAGE
420 bool
421
Ronald G. Minnich466ca2c2019-10-22 02:02:24 +0000422config CONFIGURABLE_RAMSTAGE
423 bool "Enable a configurable ramstage."
424 default y if ARCH_X86
Subrata Banik37bead62020-02-09 19:13:52 +0530425 depends on HAVE_CONFIGURABLE_RAMSTAGE
Ronald G. Minnich466ca2c2019-10-22 02:02:24 +0000426 help
427 A configurable ramstage allows you to select which parts of the ramstage
428 to run. Currently, we can only select a minimal PCI scanning step.
429 The minimal PCI scanning will only check those parts that are enabled
430 in the devicetree.cb. By convention none of those devices should be bridges.
431
432config MINIMAL_PCI_SCANNING
433 bool "Enable minimal PCI scanning"
Subrata Banik1cb26a62020-02-09 19:35:16 +0530434 depends on CONFIGURABLE_RAMSTAGE && PCI
Ronald G. Minnich466ca2c2019-10-22 02:02:24 +0000435 help
Subrata Banik1cb26a62020-02-09 19:35:16 +0530436 If this option is enabled, coreboot will scan only PCI devices
Ronald G. Minnich466ca2c2019-10-22 02:02:24 +0000437 marked as mandatory in devicetree.cb
Uwe Hermannc04be932009-10-05 13:55:28 +0000438endmenu
439
Martin Roth026e4dc2015-06-19 23:17:15 -0600440menu "Mainboard"
441
Stefan Reinauera48ca842015-04-04 01:58:28 +0200442source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000443
Marshall Dawsone9375132016-09-04 08:38:33 -0600444config DEVICETREE
445 string
446 default "devicetree.cb"
447 help
448 This symbol allows mainboards to select a different file under their
449 mainboard directory for the devicetree.cb file. This allows the board
450 variants that need different devicetrees to be in the same directory.
451
452 Examples: "devicetree.variant.cb"
453 "variant/devicetree.cb"
454
Furquan Shaikhf2419982018-06-21 18:50:48 -0700455config OVERRIDE_DEVICETREE
456 string
457 default ""
458 help
459 This symbol allows variants to provide an override devicetree file to
460 override the registers and/or add new devices on top of the ones
461 provided by baseboard devicetree using CONFIG_DEVICETREE.
462
463 Examples: "devicetree.variant-override.cb"
464 "variant/devicetree-override.cb"
465
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200466config FMDFILE
467 string "fmap description file in fmd format"
Patrick Georgib8fba862020-06-17 21:06:53 +0200468 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200469 default ""
470 help
471 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
472 but in some cases more complex setups are required.
473 When an fmd is specified, it overrides the default format.
474
Arthur Heymans965881b2019-09-25 13:18:52 +0200475config CBFS_SIZE
476 hex "Size of CBFS filesystem in ROM"
477 depends on FMDFILE = ""
478 # Default value set at the end of the file
479 help
480 This is the part of the ROM actually managed by CBFS, located at the
481 end of the ROM (passed through cbfstool -o) on x86 and at at the start
482 of the ROM (passed through cbfstool -s) everywhere else. It defaults
483 to span the whole ROM on all but Intel systems that use an Intel Firmware
484 Descriptor. It can be overridden to make coreboot live alongside other
485 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
486 binaries. This symbol should only be used to generate a default FMAP and
487 is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
488
Martin Rothda1ca202015-12-26 16:51:16 -0700489endmenu
490
Martin Rothb09a5692016-01-24 19:38:33 -0700491# load site-local kconfig to allow user specific defaults and overrides
492source "site-local/Kconfig"
493
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200494config SYSTEM_TYPE_LAPTOP
Martin Roth595e7772015-04-26 18:53:26 -0600495 default n
496 bool
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200497
Duncan Laurie8312df42019-02-01 11:33:57 -0800498config SYSTEM_TYPE_TABLET
499 default n
500 bool
501
502config SYSTEM_TYPE_DETACHABLE
503 default n
504 bool
505
506config SYSTEM_TYPE_CONVERTIBLE
507 default n
508 bool
509
Werner Zehc0fb3612016-01-14 15:08:36 +0100510config CBFS_AUTOGEN_ATTRIBUTES
511 default n
512 bool
513 help
514 If this option is selected, every file in cbfs which has a constraint
515 regarding position or alignment will get an additional file attribute
516 which describes this constraint.
517
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000518menu "Chipset"
519
Duncan Lauried2119762015-06-08 18:11:56 -0700520comment "SoC"
Chris Chingaa8e5d32017-10-20 10:43:39 -0600521source "src/soc/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000522comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200523source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000524comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200525source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000526comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200527source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000528comment "Super I/O"
Omar Pakker57603e22016-07-29 23:31:45 +0200529source "src/superio/*/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000530comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200531source "src/ec/acpi/Kconfig"
532source "src/ec/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000533
Martin Roth59aa2b12015-06-20 16:17:12 -0600534source "src/southbridge/intel/common/firmware/Kconfig"
Martin Rothe1523ec2015-06-19 22:30:43 -0600535source "src/vendorcode/*/Kconfig"
Martin Roth59aa2b12015-06-20 16:17:12 -0600536
Martin Rothe1523ec2015-06-19 22:30:43 -0600537source "src/arch/*/Kconfig"
538
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000539endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000540
Stefan Reinauera48ca842015-04-04 01:58:28 +0200541source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800542
Rudolf Marekd9c25492010-05-16 15:31:53 +0000543menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200544source "src/drivers/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800545source "src/drivers/*/*/Kconfig"
Lee Leahy48dbc662017-05-08 16:56:03 -0700546source "src/commonlib/storage/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000547endmenu
548
Philipp Deppenwiese1899fbe2017-10-16 17:09:33 +0200549menu "Security"
550
551source "src/security/Kconfig"
Wim Vervoorne32d16f2019-11-14 14:10:28 +0100552source "src/vendorcode/eltan/security/Kconfig"
Philipp Deppenwiese1899fbe2017-10-16 17:09:33 +0200553
554endmenu
555
Martin Roth09210a12016-05-17 11:28:23 -0600556source "src/acpi/Kconfig"
557
Aaron Durbin4a36c4e2016-08-11 11:02:26 -0500558# This option is for the current boards/chipsets where SPI flash
559# is not the boot device. Currently nearly all boards/chipsets assume
560# SPI flash is the boot device.
561config BOOT_DEVICE_NOT_SPI_FLASH
562 bool
563 default n
564
565config BOOT_DEVICE_SPI_FLASH
566 bool
567 default y if !BOOT_DEVICE_NOT_SPI_FLASH
568 default n
569
Aaron Durbin16c173f2016-08-11 14:04:10 -0500570config BOOT_DEVICE_MEMORY_MAPPED
571 bool
572 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
573 default n
574 help
575 Inform system if SPI is memory-mapped or not.
576
Aaron Durbine8e118d2016-08-12 15:00:10 -0500577config BOOT_DEVICE_SUPPORTS_WRITES
578 bool
579 default n
580 help
581 Indicate that the platform has writable boot device
582 support.
583
Patrick Georgi0770f252015-04-22 13:28:21 +0200584config RTC
585 bool
586 default n
587
Patrick Georgi0588d192009-08-12 15:00:51 +0000588config HEAP_SIZE
589 hex
Marty E. Plummer0987e432019-04-22 20:46:27 -0500590 default 0x100000 if FLATTENED_DEVICE_TREE
Myles Watson04000f42009-10-16 19:12:49 +0000591 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000592
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700593config STACK_SIZE
594 hex
Julius Werner66a476a2015-10-12 16:45:21 -0700595 default 0x1000 if ARCH_X86
596 default 0x0
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700597
Patrick Georgi0588d192009-08-12 15:00:51 +0000598config MAX_CPUS
599 int
600 default 1
601
Stefan Reinauera48ca842015-04-04 01:58:28 +0200602source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000603
604config HAVE_ACPI_RESUME
605 bool
606 default n
607
Wim Vervoornbccc7e72020-01-15 11:31:25 +0100608config DISABLE_ACPI_HIBERNATE
609 bool
610 default n
611 help
612 Removes S4 from the available sleepstates
613
Aaron Durbin87c9fae2016-01-22 15:26:04 -0600614config RESUME_PATH_SAME_AS_BOOT
615 bool
616 default y if ARCH_X86
617 depends on HAVE_ACPI_RESUME
618 help
619 This option indicates that when a system resumes it takes the
620 same path as a regular boot. e.g. an x86 system runs from the
621 reset vector at 0xfffffff0 on both resume and warm/cold boot.
622
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300623config NO_MONOTONIC_TIMER
Aaron Durbina4217912013-04-29 22:31:51 -0500624 def_bool n
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300625
626config HAVE_MONOTONIC_TIMER
627 bool
628 depends on !NO_MONOTONIC_TIMER
Kyösti Mälkkib28b6b52019-07-01 15:38:25 +0300629 default y
Aaron Durbina4217912013-04-29 22:31:51 -0500630 help
631 The board/chipset provides a monotonic timer.
632
Aaron Durbine5e36302014-09-25 10:05:15 -0500633config GENERIC_UDELAY
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300634 bool
Aaron Durbine5e36302014-09-25 10:05:15 -0500635 depends on HAVE_MONOTONIC_TIMER
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300636 default y if !ARCH_X86
Aaron Durbine5e36302014-09-25 10:05:15 -0500637 help
638 The board/chipset uses a generic udelay function utilizing the
639 monotonic timer.
640
Aaron Durbin340ca912013-04-30 09:58:12 -0500641config TIMER_QUEUE
642 def_bool n
643 depends on HAVE_MONOTONIC_TIMER
644 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300645 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500646
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500647config COOP_MULTITASKING
648 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500649 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500650 help
651 Cooperative multitasking allows callbacks to be multiplexed on the
652 main thread of ramstage. With this enabled it allows for multiple
653 execution paths to take place when they have udelay() calls within
654 their code.
655
656config NUM_THREADS
657 int
658 default 4
659 depends on COOP_MULTITASKING
660 help
661 How many execution threads to cooperatively multitask with.
662
Patrick Georgi0588d192009-08-12 15:00:51 +0000663config HAVE_OPTION_TABLE
664 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000665 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000666 help
667 This variable specifies whether a given board has a cmos.layout
668 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000669 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000670
Patrick Georgi0588d192009-08-12 15:00:51 +0000671config PCI_IO_CFG_EXT
672 bool
673 default n
674
675config IOAPIC
676 bool
677 default n
678
Myles Watson45bb25f2009-09-22 18:49:08 +0000679config USE_WATCHDOG_ON_BOOT
680 bool
681 default n
682
Myles Watson45bb25f2009-09-22 18:49:08 +0000683config GFXUMA
684 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000685 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000686 help
687 Enable Unified Memory Architecture for graphics.
688
Myles Watsonb8e20272009-10-15 13:35:47 +0000689config HAVE_MP_TABLE
690 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000691 help
692 This variable specifies whether a given board has MP table support.
693 It is usually set in mainboard/*/Kconfig.
694 Whether or not the MP table is actually generated by coreboot
695 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000696
697config HAVE_PIRQ_TABLE
698 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000699 help
700 This variable specifies whether a given board has PIRQ table support.
701 It is usually set in mainboard/*/Kconfig.
702 Whether or not the PIRQ table is actually generated by coreboot
703 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000704
Aaron Durbin9420a522015-11-17 16:31:00 -0600705config ACPI_NHLT
706 bool
707 default n
708 help
709 Build support for NHLT (non HD Audio) ACPI table generation.
710
Myles Watsond73c1b52009-10-26 15:14:07 +0000711#These Options are here to avoid "undefined" warnings.
712#The actual selection and help texts are in the following menu.
713
Uwe Hermann168b11b2009-10-07 16:15:40 +0000714menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000715
Myles Watsonb8e20272009-10-15 13:35:47 +0000716config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800717 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
718 bool
719 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000720 help
721 Generate an MP table (conforming to the Intel MultiProcessor
722 specification 1.4) for this board.
723
724 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000725
Myles Watsonb8e20272009-10-15 13:35:47 +0000726config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800727 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
728 bool
729 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000730 help
731 Generate a PIRQ table for this board.
732
733 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000734
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200735config GENERATE_SMBIOS_TABLES
736 depends on ARCH_X86
737 bool "Generate SMBIOS tables"
738 default y
739 help
740 Generate SMBIOS tables for this board.
741
742 If unsure, say Y.
743
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200744config SMBIOS_PROVIDED_BY_MOBO
745 bool
746 default n
747
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200748config MAINBOARD_SERIAL_NUMBER
Nico Huberebd8a4f2017-11-01 09:49:16 +0100749 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
750 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200751 depends on GENERATE_SMBIOS_TABLES
752 default "123456789"
Martin Roth595e7772015-04-26 18:53:26 -0600753 help
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200754 The Serial Number to store in SMBIOS structures.
755
756config MAINBOARD_VERSION
Nico Huberebd8a4f2017-11-01 09:49:16 +0100757 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
758 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200759 depends on GENERATE_SMBIOS_TABLES
760 default "1.0"
761 help
762 The Version Number to store in SMBIOS structures.
763
764config MAINBOARD_SMBIOS_MANUFACTURER
Nico Huberebd8a4f2017-11-01 09:49:16 +0100765 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
766 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200767 depends on GENERATE_SMBIOS_TABLES
768 default MAINBOARD_VENDOR
769 help
770 Override the default Manufacturer stored in SMBIOS structures.
771
772config MAINBOARD_SMBIOS_PRODUCT_NAME
Nico Huberebd8a4f2017-11-01 09:49:16 +0100773 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
774 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200775 depends on GENERATE_SMBIOS_TABLES
776 default MAINBOARD_PART_NUMBER
777 help
778 Override the default Product name stored in SMBIOS structures.
779
Johnny Linc746a742020-06-03 11:44:22 +0800780config VPD_SMBIOS_VERSION
781 bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'"
782 default n
783 depends on VPD && GENERATE_SMBIOS_TABLES
784 help
785 Selecting this option will read firmware_version from
786 VPD_RO and override SMBIOS type 0 version. One special
787 scenario of using this feature is to assign a BIOS version
788 to a coreboot image without the need to rebuild from source.
789
Myles Watson45bb25f2009-09-22 18:49:08 +0000790endmenu
791
Martin Roth21c06502016-02-04 19:52:27 -0700792source "payloads/Kconfig"
Peter Stugea758ca22009-09-17 16:21:31 +0000793
Uwe Hermann168b11b2009-10-07 16:15:40 +0000794menu "Debugging"
795
Nico Huberd67edca2018-11-13 19:28:07 +0100796comment "CPU Debug Settings"
Arthur Heymansaae81902019-11-04 21:50:21 +0100797source "src/cpu/*/Kconfig.debug_cpu"
Nico Huberd67edca2018-11-13 19:28:07 +0100798
Arthur Heymans71bd7e42019-10-20 14:20:53 +0200799comment "BLOB Debug Settings"
800source "src/drivers/intel/fsp*/Kconfig.debug_blob"
801
Nico Huberd67edca2018-11-13 19:28:07 +0100802comment "General Debug Settings"
803
Uwe Hermann168b11b2009-10-07 16:15:40 +0000804# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000805config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000806 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200807 default n
Arthur Heymans8e980132019-11-04 09:33:04 +0100808 depends on DRIVERS_UART
Patrick Georgi0588d192009-08-12 15:00:51 +0000809 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000810 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000811 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000812
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200813config GDB_WAIT
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100814 bool "Wait for a GDB connection in the ramstage"
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200815 default n
816 depends on GDB_STUB
817 help
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100818 If enabled, coreboot will wait for a GDB connection in the ramstage.
819
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200820
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800821config FATAL_ASSERTS
822 bool "Halt when hitting a BUG() or assertion error"
823 default n
824 help
825 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
826
Nico Huber371a6672018-11-13 22:06:40 +0100827config HAVE_DEBUG_GPIO
828 bool
829
830config DEBUG_GPIO
831 bool "Output verbose GPIO debug messages"
832 depends on HAVE_DEBUG_GPIO
833
Stefan Reinauerfe422182012-05-02 16:33:18 -0700834config DEBUG_CBFS
835 bool "Output verbose CBFS debug messages"
836 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700837 help
838 This option enables additional CBFS related debug messages.
839
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000840config HAVE_DEBUG_RAM_SETUP
841 def_bool n
842
Uwe Hermann01ce6012010-03-05 10:03:50 +0000843config DEBUG_RAM_SETUP
844 bool "Output verbose RAM init debug messages"
845 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000846 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000847 help
848 This option enables additional RAM init related debug messages.
849 It is recommended to enable this when debugging issues on your
850 board which might be RAM init related.
851
852 Note: This option will increase the size of the coreboot image.
853
854 If unsure, say N.
855
Myles Watson80e914f2010-06-01 19:25:31 +0000856config DEBUG_PIRQ
857 bool "Check PIRQ table consistency"
858 default n
859 depends on GENERATE_PIRQ_TABLE
860 help
861 If unsure, say N.
862
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000863config HAVE_DEBUG_SMBUS
864 def_bool n
865
Uwe Hermann01ce6012010-03-05 10:03:50 +0000866config DEBUG_SMBUS
867 bool "Output verbose SMBus debug messages"
868 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000869 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000870 help
871 This option enables additional SMBus (and SPD) debug messages.
872
873 Note: This option will increase the size of the coreboot image.
874
875 If unsure, say N.
876
877config DEBUG_SMI
878 bool "Output verbose SMI debug messages"
879 default n
880 depends on HAVE_SMI_HANDLER
Nico Huber9e53db42018-06-05 22:34:08 +0200881 select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
Uwe Hermann01ce6012010-03-05 10:03:50 +0000882 help
883 This option enables additional SMI related debug messages.
884
885 Note: This option will increase the size of the coreboot image.
886
887 If unsure, say N.
888
Kyösti Mälkki94464472020-06-13 13:45:42 +0300889config DEBUG_PERIODIC_SMI
890 bool "Trigger SMI periodically"
891 depends on DEBUG_SMI
892
Uwe Hermanna953f372010-11-10 00:14:32 +0000893# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
894# printk(BIOS_DEBUG, ...) calls.
895config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800896 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
897 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000898 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000899 help
900 This option enables additional malloc related debug messages.
901
902 Note: This option will increase the size of the coreboot image.
903
904 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300905
Kyösti Mälkki66277952018-12-31 15:22:34 +0200906config DEBUG_CONSOLE_INIT
907 bool "Debug console initialisation code"
908 default n
909 help
910 With this option printk()'s are attempted before console hardware
911 initialisation has been completed. Your mileage may vary.
912
913 Typically you will need to modify source in console_hw_init() such
914 that a working console appears before the one you want to debug.
915
916 If unsure, say N.
917
Uwe Hermanna953f372010-11-10 00:14:32 +0000918# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
919# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000920config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800921 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
922 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000923 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000924 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000925 help
926 This option enables additional x86emu related debug messages.
927
928 Note: This option will increase the time to emulate a ROM.
929
930 If unsure, say N.
931
Uwe Hermann01ce6012010-03-05 10:03:50 +0000932config X86EMU_DEBUG
933 bool "Output verbose x86emu debug messages"
934 default n
935 depends on PCI_OPTION_ROM_RUN_YABEL
936 help
937 This option enables additional x86emu related debug messages.
938
939 Note: This option will increase the size of the coreboot image.
940
941 If unsure, say N.
942
943config X86EMU_DEBUG_JMP
944 bool "Trace JMP/RETF"
945 default n
946 depends on X86EMU_DEBUG
947 help
948 Print information about JMP and RETF opcodes from x86emu.
949
950 Note: This option will increase the size of the coreboot image.
951
952 If unsure, say N.
953
954config X86EMU_DEBUG_TRACE
955 bool "Trace all opcodes"
956 default n
957 depends on X86EMU_DEBUG
958 help
959 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000960
Uwe Hermann01ce6012010-03-05 10:03:50 +0000961 WARNING: This will produce a LOT of output and take a long time.
962
963 Note: This option will increase the size of the coreboot image.
964
965 If unsure, say N.
966
967config X86EMU_DEBUG_PNP
968 bool "Log Plug&Play accesses"
969 default n
970 depends on X86EMU_DEBUG
971 help
972 Print Plug And Play accesses made by option ROMs.
973
974 Note: This option will increase the size of the coreboot image.
975
976 If unsure, say N.
977
978config X86EMU_DEBUG_DISK
979 bool "Log Disk I/O"
980 default n
981 depends on X86EMU_DEBUG
982 help
983 Print Disk I/O related messages.
984
985 Note: This option will increase the size of the coreboot image.
986
987 If unsure, say N.
988
989config X86EMU_DEBUG_PMM
990 bool "Log PMM"
991 default n
992 depends on X86EMU_DEBUG
993 help
994 Print messages related to POST Memory Manager (PMM).
995
996 Note: This option will increase the size of the coreboot image.
997
998 If unsure, say N.
999
1000
1001config X86EMU_DEBUG_VBE
1002 bool "Debug VESA BIOS Extensions"
1003 default n
1004 depends on X86EMU_DEBUG
1005 help
1006 Print messages related to VESA BIOS Extension (VBE) functions.
1007
1008 Note: This option will increase the size of the coreboot image.
1009
1010 If unsure, say N.
1011
1012config X86EMU_DEBUG_INT10
1013 bool "Redirect INT10 output to console"
1014 default n
1015 depends on X86EMU_DEBUG
1016 help
1017 Let INT10 (i.e. character output) calls print messages to debug output.
1018
1019 Note: This option will increase the size of the coreboot image.
1020
1021 If unsure, say N.
1022
1023config X86EMU_DEBUG_INTERRUPTS
1024 bool "Log intXX calls"
1025 default n
1026 depends on X86EMU_DEBUG
1027 help
1028 Print messages related to interrupt handling.
1029
1030 Note: This option will increase the size of the coreboot image.
1031
1032 If unsure, say N.
1033
1034config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1035 bool "Log special memory accesses"
1036 default n
1037 depends on X86EMU_DEBUG
1038 help
1039 Print messages related to accesses to certain areas of the virtual
1040 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1041
1042 Note: This option will increase the size of the coreboot image.
1043
1044 If unsure, say N.
1045
1046config X86EMU_DEBUG_MEM
1047 bool "Log all memory accesses"
1048 default n
1049 depends on X86EMU_DEBUG
1050 help
1051 Print memory accesses made by option ROM.
1052 Note: This also includes accesses to fetch instructions.
1053
1054 Note: This option will increase the size of the coreboot image.
1055
1056 If unsure, say N.
1057
1058config X86EMU_DEBUG_IO
1059 bool "Log IO accesses"
1060 default n
1061 depends on X86EMU_DEBUG
1062 help
1063 Print I/O accesses made by option ROM.
1064
1065 Note: This option will increase the size of the coreboot image.
1066
1067 If unsure, say N.
1068
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001069config X86EMU_DEBUG_TIMINGS
1070 bool "Output timing information"
1071 default n
Kyösti Mälkki91945fb2019-07-10 15:10:22 +03001072 depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001073 help
1074 Print timing information needed by i915tool.
1075
1076 If unsure, say N.
1077
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -07001078config DEBUG_SPI_FLASH
1079 bool "Output verbose SPI flash debug messages"
1080 default n
1081 depends on SPI_FLASH
1082 help
1083 This option enables additional SPI flash related debug messages.
1084
Stefan Reinauer8e073822012-04-04 00:07:22 +02001085if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1086# Only visible with the right southbridge and loglevel.
1087config DEBUG_INTEL_ME
1088 bool "Verbose logging for Intel Management Engine"
1089 default n
1090 help
1091 Enable verbose logging for Intel Management Engine driver that
1092 is present on Intel 6-series chipsets.
1093endif
1094
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001095config TRACE
1096 bool "Trace function calls"
1097 default n
1098 help
1099 If enabled, every function will print information to console once
1100 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1101 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
Ben Gardner8420ad42015-11-18 10:46:53 -06001102 of calling function. Please note some printk related functions
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001103 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -08001104
1105config DEBUG_COVERAGE
1106 bool "Debug code coverage"
1107 default n
1108 depends on COVERAGE
1109 help
1110 If enabled, the code coverage hooks in coreboot will output some
1111 information about the coverage data that is dumped.
1112
Jonathan Neuschäferfc04f9b2016-06-29 21:59:32 +02001113config DEBUG_BOOT_STATE
1114 bool "Debug boot state machine"
1115 default n
1116 help
1117 Control debugging of the boot state machine. When selected displays
1118 the state boundaries in ramstage.
1119
Nico Hubere84e62542016-10-05 17:43:56 +02001120config DEBUG_ADA_CODE
1121 bool "Compile debug code in Ada sources"
1122 default n
1123 help
1124 Add the compiler switch `-gnata` to compile code guarded by
1125 `pragma Debug`.
1126
Simon Glass46255f72018-07-12 15:26:07 -06001127config HAVE_EM100_SUPPORT
1128 bool "Platform can support the Dediprog EM100 SPI emulator"
1129 help
1130 This is enabled by platforms which can support using the EM100.
1131
1132config EM100
1133 bool "Configure image for EM100 usage"
1134 depends on HAVE_EM100_SUPPORT
1135 help
1136 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1137 over USB. However it only supports a maximum SPI clock of 20MHz and
1138 single data output. Enable this option to use a 20MHz SPI clock and
1139 disable "Dual Output Fast Read" Support.
1140
1141 On AMD platforms this changes the SPI speed at run-time if the
1142 mainboard code supports this. On supported Intel platforms this works
1143 by changing the settings in the descriptor.bin file.
1144
Uwe Hermann168b11b2009-10-07 16:15:40 +00001145endmenu
1146
Martin Roth8e4aafb2016-12-15 15:25:15 -07001147###############################################################################
1148# Set variables with no prompt - these can be set anywhere, and putting at
1149# the end of this file gives the most flexibility.
Nico Huber3db76532017-05-18 18:07:34 +02001150
1151source "src/lib/Kconfig"
1152
Myles Watson2e672732009-11-12 16:38:03 +00001153config WARNINGS_ARE_ERRORS
1154 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001155 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001156
Peter Stuge51eafde2010-10-13 06:23:02 +00001157# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1158# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1159# mutually exclusive. One of these options must be selected in the
1160# mainboard Kconfig if the chipset supports enabling and disabling of
1161# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1162# in mainboard/Kconfig to know if the button should be enabled or not.
1163
1164config POWER_BUTTON_DEFAULT_ENABLE
1165 def_bool n
1166 help
1167 Select when the board has a power button which can optionally be
1168 disabled by the user.
1169
1170config POWER_BUTTON_DEFAULT_DISABLE
1171 def_bool n
1172 help
1173 Select when the board has a power button which can optionally be
1174 enabled by the user, e.g. when the board ships with a jumper over
1175 the power switch contacts.
1176
1177config POWER_BUTTON_FORCE_ENABLE
1178 def_bool n
1179 help
1180 Select when the board requires that the power button is always
1181 enabled.
1182
1183config POWER_BUTTON_FORCE_DISABLE
1184 def_bool n
1185 help
1186 Select when the board requires that the power button is always
1187 disabled, e.g. when it has been hardwired to ground.
1188
1189config POWER_BUTTON_IS_OPTIONAL
1190 bool
1191 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1192 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1193 help
1194 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001195
1196config REG_SCRIPT
1197 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001198 default n
1199 help
1200 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001201
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001202config MAX_REBOOT_CNT
1203 int
1204 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001205 help
1206 Internal option that sets the maximum number of bootblock executions allowed
1207 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001208 and switching to the fallback image.
Martin Roth59ff3402016-02-09 09:06:46 -07001209
Martin Roth8e4aafb2016-12-15 15:25:15 -07001210config UNCOMPRESSED_RAMSTAGE
1211 bool
1212
1213config NO_XIP_EARLY_STAGES
1214 bool
1215 default n if ARCH_X86
1216 default y
1217 help
1218 Identify if early stages are eXecute-In-Place(XIP).
1219
Martin Roth8e4aafb2016-12-15 15:25:15 -07001220config EARLY_CBMEM_LIST
1221 bool
1222 default n
1223 help
1224 Enable display of CBMEM during romstage and postcar.
1225
1226config RELOCATABLE_MODULES
1227 bool
1228 help
1229 If RELOCATABLE_MODULES is selected then support is enabled for
1230 building relocatable modules in the RAM stage. Those modules can be
1231 loaded anywhere and all the relocations are handled automatically.
1232
Martin Roth8e4aafb2016-12-15 15:25:15 -07001233config GENERIC_GPIO_LIB
1234 bool
1235 help
1236 If enabled, compile the generic GPIO library. A "generic" GPIO
1237 implies configurability usually found on SoCs, particularly the
1238 ability to control internal pull resistors.
1239
Martin Roth8e4aafb2016-12-15 15:25:15 -07001240config BOOTBLOCK_CUSTOM
1241 # To be selected by arch, SoC or mainboard if it does not want use the normal
1242 # src/lib/bootblock.c#main() C entry point.
1243 bool
1244
Furquan Shaikh46514c22020-06-11 11:59:07 -07001245config MEMLAYOUT_LD_FILE
1246 string
Patrick Georgib8fba862020-06-17 21:06:53 +02001247 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld"
Furquan Shaikh46514c22020-06-11 11:59:07 -07001248 help
1249 This variable allows SoC/mainboard to supply in a custom linker file
1250 if required. This determines the linker file used for all the stages
1251 (bootblock, romstage, verstage, ramstage, postcar) in
1252 src/arch/${ARCH}/Makefile.inc.
1253
Martin Roth75e5cb72016-12-15 15:05:37 -07001254###############################################################################
1255# Set default values for symbols created before mainboards. This allows the
1256# option to be displayed in the general menu, but the default to be loaded in
1257# the mainboard if desired.
1258config COMPRESS_RAMSTAGE
1259 default y if !UNCOMPRESSED_RAMSTAGE
1260
1261config COMPRESS_PRERAM_STAGES
1262 depends on !ARCH_X86
1263 default y
1264
1265config INCLUDE_CONFIG_FILE
1266 default y
1267
Martin Roth75e5cb72016-12-15 15:05:37 -07001268config BOOTSPLASH_FILE
1269 depends on BOOTSPLASH_IMAGE
1270 default "bootsplash.jpg"
1271
1272config CBFS_SIZE
1273 default ROM_SIZE
Subrata Banikb5962a92019-06-08 12:29:02 +05301274
1275config HAVE_BOOTBLOCK
1276 bool
1277 default y
1278
1279config HAVE_VERSTAGE
1280 bool
1281 depends on VBOOT_SEPARATE_VERSTAGE
1282 default y
1283
1284config HAVE_ROMSTAGE
1285 bool
1286 default y
1287
Subrata Banikb5962a92019-06-08 12:29:02 +05301288config HAVE_RAMSTAGE
1289 bool
1290 default n if RAMPAYLOAD
1291 default y