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Tan, Lean Sheng05dfe312020-08-25 20:40:17 -07001config SOC_INTEL_ELKHARTLAKE
2 bool
3 help
4 Intel Elkhartlake support
5
6if SOC_INTEL_ELKHARTLAKE
7
8config CPU_SPECIFIC_OPTIONS
9 def_bool y
10 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Angel Ponsa32df262020-09-25 10:20:11 +020011 select ARCH_ALL_STAGES_X86_32
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -070012 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
13 select BOOT_DEVICE_SUPPORTS_WRITES
14 select CACHE_MRC_SETTINGS
15 select CPU_INTEL_COMMON
16 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
17 select FSP_COMPRESS_FSP_S_LZ4
18 select FSP_M_XIP
19 select GENERIC_GPIO_LIB
20 select HAVE_FSP_GOP
21 select INTEL_DESCRIPTOR_MODE_CAPABLE
22 select HAVE_SMI_HANDLER
23 select IDT_IN_EVERY_STAGE
24 select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
25 select INTEL_GMA_ACPI
26 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
27 select IOAPIC
28 select MRC_SETTINGS_PROTECT
29 select PARALLEL_MP
30 select PARALLEL_MP_AP_WORK
31 select MICROCODE_BLOB_UNDISCLOSED
32 select PLATFORM_USES_FSP2_2
33 select FSP_PEIM_TO_PEIM_INTERFACE
34 select REG_SCRIPT
35 select PMC_GLOBAL_RESET_ENABLE_LOCK
36 select CPU_INTEL_COMMON_SMM
37 select SOC_INTEL_COMMON
38 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
39 select SOC_INTEL_COMMON_BLOCK
40 select SOC_INTEL_COMMON_BLOCK_ACPI
41 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
42 select SOC_INTEL_COMMON_BLOCK_CPU
43 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
44 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
45 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
46 select SOC_INTEL_COMMON_BLOCK_HDA
47 select SOC_INTEL_COMMON_BLOCK_SA
48 select SOC_INTEL_COMMON_BLOCK_SCS
49 select SOC_INTEL_COMMON_BLOCK_SMM
50 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
51 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
52 select SOC_INTEL_COMMON_PCH_BASE
53 select SOC_INTEL_COMMON_RESET
54 select SOC_INTEL_COMMON_BLOCK_CAR
55 select SSE2
56 select SUPPORT_CPU_UCODE_IN_CBFS
57 select TSC_MONOTONIC_TIMER
58 select UDELAY_TSC
59 select UDK_202005_BINDING
60 select DISPLAY_FSP_VERSION_INFO
61 select HECI_DISABLE_USING_SMM
62
63config DCACHE_RAM_BASE
64 default 0xfef00000
65
66config DCACHE_RAM_SIZE
67 default 0x80000
68 help
69 The size of the cache-as-ram region required during bootblock
70 and/or romstage.
71
72config DCACHE_BSP_STACK_SIZE
73 hex
74 default 0x30400
75 help
76 The amount of anticipated stack usage in CAR by bootblock and
77 other stages. In the case of FSP_USES_CB_STACK default value
78 will be sum of FSP-M stack requirement(192 KiB) and CB romstage
79 stack requirement(~1KiB).
80
81config FSP_TEMP_RAM_SIZE
82 hex
83 default 0x20000
84 help
85 The amount of anticipated heap usage in CAR by FSP.
86 Refer to Platform FSP integration guide document to know
87 the exact FSP requirement for Heap setup.
88
89config IFD_CHIPSET
90 string
91 default "ehl"
92
93config IED_REGION_SIZE
94 hex
95 default 0x400000
96
97config HEAP_SIZE
98 hex
99 default 0x8000
100
101config MAX_ROOT_PORTS
102 int
103 default 8
104
105config MAX_PCIE_CLOCKS
106 int
107 default 6
108
109config SMM_TSEG_SIZE
110 hex
111 default 0x800000
112
113config SMM_RESERVED_SIZE
114 hex
115 default 0x200000
116
117config PCR_BASE_ADDRESS
118 hex
119 default 0xfd000000
120 help
121 This option allows you to select MMIO Base Address of sideband bus.
122
123config MMCONF_BASE_ADDRESS
124 hex
125 default 0xc0000000
126
127config CPU_BCLK_MHZ
128 int
129 default 100
130
131config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
132 int
133 default 120
134
135config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
136 int
137 default 133
138
139config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
140 int
141 default 3
142
143config SOC_INTEL_I2C_DEV_MAX
144 int
145 default 6
146
147config SOC_INTEL_UART_DEV_MAX
148 int
149 default 3
150
151config CONSOLE_UART_BASE_ADDRESS
152 hex
153 default 0xfe032000
154 depends on INTEL_LPSS_UART_FOR_CONSOLE
155
156# Clock divider parameters for 115200 baud rate
157# Baudrate = (UART source clcok * M) /(N *16)
158# EHL UART source clock: 100MHz
159config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
160 hex
161 default 0x30
162
163config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
164 hex
165 default 0xc35
166
167config CHROMEOS
168 select CHROMEOS_RAMOOPS_DYNAMIC
169
170config VBOOT
171 select VBOOT_SEPARATE_VERSTAGE
172 select VBOOT_MUST_REQUEST_DISPLAY
173 select VBOOT_STARTS_IN_BOOTBLOCK
174 select VBOOT_VBNV_CMOS
175 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
176
177config C_ENV_BOOTBLOCK_SIZE
178 hex
179 default 0xC000
180
181config CBFS_SIZE
182 hex
183 default 0x200000
184
185config FSP_HEADER_PATH
186 default "src/vendorcode/intel/fsp/fsp2_0/elkhartlake/"
187
188config FSP_FD_PATH
189 default "3rdparty/fsp/ElkhartLakeFspBinPkg/Fsp.fd"
190
191config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT
192 int "Debug Consent for EHL"
193 # USB DBC is more common for developers so make this default to 3 if
194 # SOC_INTEL_DEBUG_CONSENT=y
195 default 3 if SOC_INTEL_DEBUG_CONSENT
196 default 0
197 help
198 This is to control debug interface on SOC.
199 Setting non-zero value will allow to use DBC or DCI to debug SOC.
200 PlatformDebugConsent in FspmUpd.h has the details.
201
202 Desired platform debug type are
203 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
204 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
205 6:Enable (2-wire DCI OOB), 7:Manual
206
207config PRERAM_CBMEM_CONSOLE_SIZE
208 hex
209 default 0x1400
210endif