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Felix Held4a8cd722020-04-18 22:26:39 +02001# SPDX-License-Identifier: GPL-2.0-only
Marc Jones24484842017-05-04 21:17:45 -06002
Marshall Dawson68519222019-11-25 11:36:15 -07003config SOC_AMD_STONEYRIDGE
4 bool
5 help
6 AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh.
7
8if SOC_AMD_STONEYRIDGE
9
Marc Jones21cde8b2017-05-07 16:47:36 -060010config CPU_SPECIFIC_OPTIONS
11 def_bool y
Angel Ponsa32df262020-09-25 10:20:11 +020012 select ARCH_ALL_STAGES_X86_32
Marshall Dawson82145a12017-10-20 12:36:35 -060013 select X86_AMD_FIXED_MTRRS
Marshall Dawson68592c32017-11-06 10:56:52 -070014 select ACPI_AMD_HARDWARE_SLEEP_VALUES
Aaron Durbin51e4c1a2018-01-24 17:42:51 -070015 select COLLECT_TIMESTAMPS_NO_TSC
Chris Ching6fc39d42017-12-20 16:06:03 -070016 select DRIVERS_I2C_DESIGNWARE
Marc Jones9156cac2017-07-12 11:05:38 -060017 select GENERIC_GPIO_LIB
Aaron Durbin51e4c1a2018-01-24 17:42:51 -070018 select GENERIC_UDELAY
Marc Jones24484842017-05-04 21:17:45 -060019 select IOAPIC
Angel Ponsb74975e2020-07-13 01:12:57 +020020 select HAVE_CF9_RESET
Marc Jones24484842017-05-04 21:17:45 -060021 select HAVE_USBDEBUG_OPTIONS
Richard Spiegelbf171242019-08-21 10:09:51 -070022 select SOC_AMD_COMMON_BLOCK_SPI
Marc Jones21cde8b2017-05-07 16:47:36 -060023 select TSC_SYNC_LFENCE
Marc Jones1587dc82017-05-15 18:55:11 -060024 select SOC_AMD_PI
Marshall Dawson68243a52017-06-15 16:59:20 -060025 select SOC_AMD_COMMON
26 select SOC_AMD_COMMON_BLOCK
Marshall Dawsonec63a712019-05-03 12:55:16 -060027 select SOC_AMD_COMMON_BLOCK_IOMMU
Marshall Dawson69486ca2019-05-02 12:03:45 -060028 select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Marshall Dawson251d3052019-05-02 17:27:57 -060029 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
Marshall Dawson3ce03602019-05-03 10:20:44 -060030 select SOC_AMD_COMMON_BLOCK_ACPI
Marshall Dawson6ab5ed32019-05-29 09:24:18 -060031 select SOC_AMD_COMMON_BLOCK_LPC
Richard Spiegel2bbc3dc2017-12-06 16:14:58 -070032 select SOC_AMD_COMMON_BLOCK_PCI
Marshall Dawson43c26cb2019-05-03 12:42:29 -060033 select SOC_AMD_COMMON_BLOCK_HDA
Marshall Dawsonaa67def2019-05-03 16:10:34 -060034 select SOC_AMD_COMMON_BLOCK_SATA
Richard Spiegel19f67a32017-12-08 18:16:02 -070035 select SOC_AMD_COMMON_BLOCK_PI
Marshall Dawsond6b72362020-03-05 11:44:24 -070036 select SOC_AMD_COMMON_BLOCK_PSP_GEN1
Marshall Dawson9df969a2017-07-25 18:46:46 -060037 select SOC_AMD_COMMON_BLOCK_CAR
Kyösti Mälkkia8eb4772018-06-28 17:23:27 +030038 select SOC_AMD_COMMON_BLOCK_S3
Aaron Durbin3d2e18a2020-01-28 11:20:05 -070039 select SOC_AMD_COMMON_BLOCK_SMBUS
John E. Kabat Jraf327702017-11-29 18:49:37 -070040 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
Marc Jones4c887ea2018-04-25 16:43:18 -060041 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060042 select PARALLEL_MP
Marc Jones33eef132017-10-26 16:50:42 -060043 select PARALLEL_MP_AP_WORK
Marshall Dawsonb6172112017-09-13 17:47:31 -060044 select HAVE_SMI_HANDLER
Martin Roth37b8bde2017-09-26 09:41:10 -060045 select SSE2
Marc Jones17e85ad2017-12-20 16:21:25 -070046 select RTC
Kyösti Mälkkic3c55212020-06-17 10:34:26 +030047 select ACPI_NO_SMI_GNVS
Marc Jones24484842017-05-04 21:17:45 -060048
Marshall Dawson12294d02019-11-25 07:21:18 -070049config AMD_APU_STONEYRIDGE
50 bool
51 help
52 AMD Stoney Ridge APU
53
Marshall Dawsone1988f52019-11-25 11:15:35 -070054config AMD_APU_PRAIRIEFALCON
55 bool
56 help
57 AMD Embedded Prairie Falcon APU
58
Marshall Dawson12294d02019-11-25 07:21:18 -070059config AMD_APU_MERLINFALCON
60 bool
61 help
Marshall Dawsone1988f52019-11-25 11:15:35 -070062 AMD Embedded Merlin Falcon APU
Marshall Dawson12294d02019-11-25 07:21:18 -070063
Marshall Dawson3ac0ab52019-11-24 19:03:56 -070064config AMD_APU_PKG_FP4
65 bool
66 help
67 AMD FP4 package
68
69config AMD_APU_PKG_FT4
70 bool
71 help
72 AMD FT4 package
73
74config AMD_SOC_PACKAGE
75 string
76 default "FP4" if AMD_APU_PKG_FP4
77 default "FT4" if AMD_APU_PKG_FT4
78
Marshall Dawsone7557de2017-06-09 16:35:14 -060079config VBOOT
Marshall Dawsone7557de2017-06-09 16:35:14 -060080 select VBOOT_SEPARATE_VERSTAGE
81 select VBOOT_STARTS_IN_BOOTBLOCK
Marc Jones4c887ea2018-04-25 16:43:18 -060082 select VBOOT_VBNV_CMOS
83 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Marshall Dawsone7557de2017-06-09 16:35:14 -060084
Marc Jones21cde8b2017-05-07 16:47:36 -060085# TODO: Sync these with definitions in PI vendorcode.
86# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
87# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
88
89config DCACHE_RAM_BASE
90 hex
91 default 0x30000
92
93config DCACHE_RAM_SIZE
94 hex
95 default 0x10000
96
Marshall Dawson9df969a2017-07-25 18:46:46 -060097config DCACHE_BSP_STACK_SIZE
Marshall Dawson9df969a2017-07-25 18:46:46 -060098 hex
99 default 0x4000
100 help
101 The amount of anticipated stack usage in CAR by bootblock and
102 other stages.
103
Marshall Dawson7c3f1e72017-08-24 09:59:10 -0600104config PRERAM_CBMEM_CONSOLE_SIZE
105 hex
Marshall Dawson1df6bc62017-12-19 20:41:29 -0700106 default 0x1600
Marshall Dawson7c3f1e72017-08-24 09:59:10 -0600107 help
108 Increase this value if preram cbmem console is getting truncated
109
Marc Jones21cde8b2017-05-07 16:47:36 -0600110config CPU_ADDR_BITS
111 int
112 default 48
113
Marc Jones1587dc82017-05-15 18:55:11 -0600114config BOTTOMIO_POSITION
115 hex "Bottom of 32-bit IO space"
116 default 0xD0000000
117 help
118 If PCI peripherals with big BARs are connected to the system
119 the bottom of the IO must be decreased to allocate such
120 devices.
121
122 Declare the beginning of the 128MB-aligned MMIO region. This
123 option is useful when PCI peripherals requesting large address
124 ranges are present.
125
Marc Jones1587dc82017-05-15 18:55:11 -0600126config MMCONF_BASE_ADDRESS
127 hex
128 default 0xF8000000
129
130config MMCONF_BUS_NUMBER
131 int
132 default 64
133
134config VGA_BIOS_ID
135 string
Marshall Dawson12294d02019-11-25 07:21:18 -0700136 default "1002,9874" if AMD_APU_MERLINFALCON
Marc Jones1587dc82017-05-15 18:55:11 -0600137 default "1002,98e4"
138 help
139 The default VGA BIOS PCI vendor/device ID should be set to the
140 result of the map_oprom_vendev() function in northbridge.c.
141
142config VGA_BIOS_FILE
143 string
Marshall Dawson91e7fe72019-11-24 17:19:19 -0700144 default "" if !USE_AMD_BLOBS
Marshall Dawson7987c1c2019-11-25 08:29:28 -0700145 default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON
Marshall Dawsone1988f52019-11-25 11:15:35 -0700146 default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON
147 default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE
Marc Jones1587dc82017-05-15 18:55:11 -0600148
Marshall Dawson668dea02017-11-29 09:57:15 -0700149config S3_VGA_ROM_RUN
150 bool
151 default n
152
Marc Jones1587dc82017-05-15 18:55:11 -0600153config HEAP_SIZE
154 hex
155 default 0xc0000
156
Marc Jones24484842017-05-04 21:17:45 -0600157config EHCI_BAR
158 hex
159 default 0xfef00000
160
161config STONEYRIDGE_XHCI_ENABLE
162 bool "Enable Stoney Ridge XHCI Controller"
163 default y
164 help
165 The XHCI controller must be enabled and the XHCI firmware
166 must be added in order to have USB 3.0 support configured
167 by coreboot. The OS will be responsible for enabling the XHCI
Jonathan Neuschäfer45e6c822018-12-11 17:53:07 +0100168 controller if the XHCI firmware is available but the
Marc Jones24484842017-05-04 21:17:45 -0600169 XHCI controller is not enabled by coreboot.
170
171config STONEYRIDGE_XHCI_FWM
172 bool "Add xhci firmware"
173 default y
174 help
175 Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
176
Marc Jones24484842017-05-04 21:17:45 -0600177config STONEYRIDGE_GEC_FWM
178 bool
179 default n
180 help
181 Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
182 Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
183
184config STONEYRIDGE_XHCI_FWM_FILE
185 string "XHCI firmware path and filename"
Marshall Dawson91e7fe72019-11-24 17:19:19 -0700186 default "" if !USE_AMD_BLOBS
Marshall Dawson7987c1c2019-11-25 08:29:28 -0700187 default "3rdparty/amd_blobs/stoneyridge/xhci.bin"
Marc Jones24484842017-05-04 21:17:45 -0600188 depends on STONEYRIDGE_XHCI_FWM
189
Marc Jones24484842017-05-04 21:17:45 -0600190config STONEYRIDGE_GEC_FWM_FILE
191 string "GEC firmware path and filename"
192 depends on STONEYRIDGE_GEC_FWM
193
194config AMD_PUBKEY_FILE
195 string "AMD public Key"
Marshall Dawson91e7fe72019-11-24 17:19:19 -0700196 default "" if !USE_AMD_BLOBS
Marshall Dawson7987c1c2019-11-25 08:29:28 -0700197 default "3rdparty/amd_blobs/stoneyridge/PSP/CZ/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON
Marshall Dawsone1988f52019-11-25 11:15:35 -0700198 default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_PRAIRIEFALCON
199 default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_STONEYRIDGE
Marc Jones24484842017-05-04 21:17:45 -0600200
201config STONEYRIDGE_SATA_MODE
202 int "SATA Mode"
203 default 0
204 range 0 6
205 help
206 Select the mode in which SATA should be driven.
207 The default is NATIVE.
208 0: NATIVE mode does not require a ROM.
209 2: AHCI may work with or without AHCI ROM. It depends on the payload support.
210 For example, seabios does not require the AHCI ROM.
211 3: LEGACY IDE
212 4: IDE to AHCI
213 5: AHCI7804: ROM Required, and AMD driver required in the OS.
214 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
215
216comment "NATIVE"
217 depends on STONEYRIDGE_SATA_MODE = 0
218
219comment "AHCI"
220 depends on STONEYRIDGE_SATA_MODE = 2
221
222comment "LEGACY IDE"
223 depends on STONEYRIDGE_SATA_MODE = 3
224
225comment "IDE to AHCI"
226 depends on STONEYRIDGE_SATA_MODE = 4
227
228comment "AHCI7804"
229 depends on STONEYRIDGE_SATA_MODE = 5
230
231comment "IDE to AHCI7804"
232 depends on STONEYRIDGE_SATA_MODE = 6
233
234if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
235
236config AHCI_ROM_ID
237 string "AHCI device PCI IDs"
238 default "1022,7801" if STONEYRIDGE_SATA_MODE = 2
239 default "1022,7804" if STONEYRIDGE_SATA_MODE = 5
240
241endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
242
243config STONEYRIDGE_LEGACY_FREE
244 bool "System is legacy free"
245 help
246 Select y if there is no keyboard controller in the system.
247 This sets variables in AGESA and ACPI.
248
Marc Jones24484842017-05-04 21:17:45 -0600249config SERIRQ_CONTINUOUS_MODE
250 bool
251 default n
252 help
253 Set this option to y for serial IRQ in continuous mode.
254 Otherwise it is in quiet mode.
255
256config STONEYRIDGE_ACPI_IO_BASE
257 hex
258 default 0x400
259 help
260 Base address for the ACPI registers.
261 This value must match the hardcoded value of AGESA.
262
263config STONEYRIDGE_UART
264 bool "UART controller on Stoney Ridge"
265 default n
266 select DRIVERS_UART_8250MEM
267 select DRIVERS_UART_8250MEM_32
268 select NO_UART_ON_SUPERIO
269 select UART_OVERRIDE_REFCLK
270 help
271 There are two UART controllers in Stoney Ridge.
272 The UART registers are memory-mapped. UART
273 controller 0 registers range from FEDC_6000h
274 to FEDC_6FFFh. UART controller 1 registers
275 range from FEDC_8000h to FEDC_8FFFh.
276
Arthur Heymansb5e72b62018-01-02 23:41:24 +0100277config CONSOLE_UART_BASE_ADDRESS
278 depends on CONSOLE_SERIAL
279 hex
280 default 0xfedc6000
281
Marshall Dawsonc6ef9db2017-05-14 14:16:56 -0600282config SMM_TSEG_SIZE
283 hex
Marshall Dawson0801b332017-08-25 15:29:45 -0600284 default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
Marshall Dawsonc6ef9db2017-05-14 14:16:56 -0600285 default 0x0
286
Marshall Dawsonb6172112017-09-13 17:47:31 -0600287config SMM_RESERVED_SIZE
288 hex
Marshall Dawsonfceac7e2018-05-18 14:40:53 -0600289 default 0x150000
Marshall Dawsonb6172112017-09-13 17:47:31 -0600290
Raul E Rangel846b4942018-06-12 10:43:09 -0600291config SMM_MODULE_STACK_SIZE
292 hex
293 default 0x800
294
Marc Jonese013df92017-08-23 16:28:02 -0600295config ACPI_CPU_STRING
296 string
Matt DeVillierc08d4c52020-06-20 23:45:30 -0500297 default "\\_SB.P%03d"
Marc Jonese013df92017-08-23 16:28:02 -0600298
Marshall Dawson9a32c412018-09-04 13:29:12 -0600299config ACPI_BERT
300 bool "Build ACPI BERT Table"
301 default y
302 depends on HAVE_ACPI_TABLES
303 help
304 Report Machine Check errors identified in POST to the OS in an
305 ACPI Boot Error Record Table. This option reserves an 8MB region
306 for building the error structures.
307
Marshall Dawson25eb2bc2019-03-14 12:42:46 -0600308config USE_PSPSECUREOS
Martin Rothb617e322017-09-07 13:23:55 -0600309 bool "Include PSP SecureOS blobs in AMD firmware"
310 default y
311 help
312 Include the PspSecureOs, PspTrustlet and TrustletKey binaries
313 in the amdfw section.
314
315 If unsure, answer 'y'
316
Richard Spiegel1bc578a2019-06-18 18:19:47 -0700317config SOC_AMD_PSP_SELECTABLE_SMU_FW
318 bool
Marshall Dawson12294d02019-11-25 07:21:18 -0700319 default y if AMD_APU_STONEYRIDGE
Richard Spiegel1bc578a2019-06-18 18:19:47 -0700320 help
321 Some ST implementations allow storing SMU firmware into cbfs and
322 calling the PSP to load the blobs at the proper time.
323
324 Merlin Falcon does not support it. If you are using 00670F00 SOC,
325 ask your AMD representative if it supports it or not.
326
Marshall Dawson5f0520a2017-10-30 16:11:45 -0600327config SOC_AMD_SMU_FANLESS
328 bool
329 depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
330 default n if SOC_AMD_SMU_NOTFANLESS
331 default y
332
333config SOC_AMD_SMU_FANNED
334 bool
335 depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
336 default n
337 select SOC_AMD_SMU_NOTFANLESS
338
339config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use
340 bool
341 depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
342
Martin Roth30f9b952017-10-03 15:54:45 -0600343config AMDFW_OUTSIDE_CBFS
344 bool "The AMD firmware is outside CBFS"
345 default n
346 help
347 The AMDFW (PSP) is typically locatable in cbfs. Select this
348 option to manually attach the generated amdfw.rom outside of
349 cbfs. The location is selected by the FWM position.
350
Martin Roth6d8ef242017-09-08 14:39:35 -0600351config AMD_FWM_POSITION_INDEX
352 int "Firmware Directory Table location (0 to 5)"
353 range 0 5
354 default 0 if BOARD_ROMSIZE_KB_512
355 default 1 if BOARD_ROMSIZE_KB_1024
356 default 2 if BOARD_ROMSIZE_KB_2048
357 default 3 if BOARD_ROMSIZE_KB_4096
358 default 4 if BOARD_ROMSIZE_KB_8192
359 default 5 if BOARD_ROMSIZE_KB_16384
360 help
361 Typically this is calculated by the ROM size, but there may
362 be situations where you want to put the firmware directory
363 table in a different location.
364 0: 512 KB - 0xFFFA0000
365 1: 1 MB - 0xFFF20000
366 2: 2 MB - 0xFFE20000
367 3: 4 MB - 0xFFC20000
368 4: 8 MB - 0xFF820000
369 5: 16 MB - 0xFF020000
370
371comment "AMD Firmware Directory Table set to location for 512KB ROM"
372 depends on AMD_FWM_POSITION_INDEX = 0
373comment "AMD Firmware Directory Table set to location for 1MB ROM"
374 depends on AMD_FWM_POSITION_INDEX = 1
375comment "AMD Firmware Directory Table set to location for 2MB ROM"
376 depends on AMD_FWM_POSITION_INDEX = 2
377comment "AMD Firmware Directory Table set to location for 4MB ROM"
378 depends on AMD_FWM_POSITION_INDEX = 3
379comment "AMD Firmware Directory Table set to location for 8MB ROM"
380 depends on AMD_FWM_POSITION_INDEX = 4
381comment "AMD Firmware Directory Table set to location for 16MB ROM"
382 depends on AMD_FWM_POSITION_INDEX = 5
383
Marc Jones17431ab2017-11-16 15:26:00 -0700384config DIMM_SPD_SIZE
385 int
386 default 512 # DDR4
387
Marc Jones578a79d2017-12-06 16:27:04 -0700388config RO_REGION_ONLY
389 string
390 depends on CHROMEOS
391 default "apu/amdfw"
392
Chris Ching6fc39d42017-12-20 16:06:03 -0700393config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
394 int
395 default 133
396
Richard Spiegel6a389142018-03-05 14:28:10 -0700397config MAINBOARD_POWER_RESTORE
398 def_bool n
399 help
400 This option determines what state to go to once power is restored
401 after having been lost in S0. Select this option to automatically
402 return to S0. Otherwise the system will remain in S5 once power
403 is restored.
404
Marshall Dawson68519222019-11-25 11:36:15 -0700405endif # SOC_AMD_STONEYRIDGE