Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <stddef.h> |
| 19 | #include <string.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 20 | #include <device/pci_def.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 21 | #include <spd.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 22 | #include "delay.h" |
| 23 | |
| 24 | #include "gm45.h" |
| 25 | |
| 26 | void raminit_thermal(const sysinfo_t *sysinfo) |
| 27 | { |
| 28 | const mem_clock_t freq = sysinfo->selected_timings.mem_clock; |
| 29 | int x; |
| 30 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, x) { |
| 31 | const chip_width_t width = sysinfo->dimms[x].chip_width; |
| 32 | const chip_capacity_t size = sysinfo->dimms[x].chip_capacity; |
| 33 | if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x16)) { |
| 34 | MCHBAR32(CxDTPEW(x)) = 0x0d0b0403; |
| 35 | MCHBAR32(CxDTPEW(x)+4) = 0x060d; |
| 36 | MCHBAR32(CxDTAEW(x)) = 0x2d0b221a; |
| 37 | MCHBAR32(CxDTAEW(x)+4) = 0xc779956e; |
| 38 | } else |
| 39 | if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x8)) { |
| 40 | MCHBAR32(CxDTPEW(x)) = 0x06040101; |
| 41 | MCHBAR32(CxDTPEW(x)+4) = 0x0506; |
| 42 | if (size == CHIP_CAP_2G) |
| 43 | MCHBAR32(CxDTAEW(x)) = 0xa1071416; |
| 44 | else |
| 45 | MCHBAR32(CxDTAEW(x)) = 0x1a071416; |
| 46 | MCHBAR32(CxDTAEW(x)+4) = 0x7246643f; |
| 47 | } else |
| 48 | if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x16)) { |
| 49 | MCHBAR32(CxDTPEW(x)) = 0x06030100; |
| 50 | MCHBAR32(CxDTPEW(x)+4) = 0x0506; |
| 51 | MCHBAR32(CxDTAEW(x)) = 0x3e081714; |
| 52 | MCHBAR32(CxDTAEW(x)+4) = 0xbb79a171; |
| 53 | } else |
| 54 | if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x8)) { |
| 55 | if (size <= CHIP_CAP_512M) |
| 56 | MCHBAR32(CxDTPEW(x)) = 0x05050101; |
| 57 | else |
| 58 | MCHBAR32(CxDTPEW(x)) = 0x05060101; |
| 59 | MCHBAR32(CxDTPEW(x)+4) = 0x0503; |
| 60 | if (size == CHIP_CAP_2G) { |
| 61 | MCHBAR32(CxDTAEW(x)) = 0x57051010; |
| 62 | MCHBAR32(CxDTAEW(x)+4) = 0x5fd15dde; |
| 63 | } else |
| 64 | if (size == CHIP_CAP_1G) { |
| 65 | MCHBAR32(CxDTAEW(x)) = 0x3306130e; |
| 66 | MCHBAR32(CxDTAEW(x)+4) = 0x5763485d; |
| 67 | } else |
| 68 | if (size <= CHIP_CAP_512M) { |
| 69 | MCHBAR32(CxDTAEW(x)) = 0x1e08170d; |
| 70 | MCHBAR32(CxDTAEW(x)+4) = 0x502f3827; |
| 71 | } |
| 72 | } else |
| 73 | if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x16)) { |
| 74 | MCHBAR32(CxDTPEW(x)) = 0x02000000; |
| 75 | MCHBAR32(CxDTPEW(x)+4) = 0x0402; |
| 76 | MCHBAR32(CxDTAEW(x)) = 0x46061111; |
| 77 | MCHBAR32(CxDTAEW(x)+4) = 0xb579a772; |
| 78 | } else |
| 79 | if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x8)) { |
| 80 | MCHBAR32(CxDTPEW(x)) = 0x04070101; |
| 81 | MCHBAR32(CxDTPEW(x)+4) = 0x0501; |
| 82 | if (size == CHIP_CAP_2G) { |
| 83 | MCHBAR32(CxDTAEW(x)) = 0x32040e0d; |
| 84 | MCHBAR32(CxDTAEW(x)+4) = 0x55ff59ff; |
| 85 | } else |
| 86 | if (size == CHIP_CAP_1G) { |
| 87 | MCHBAR32(CxDTAEW(x)) = 0x3f05120a; |
| 88 | MCHBAR32(CxDTAEW(x)+4) = 0x49713a6c; |
| 89 | } else |
| 90 | if (size <= CHIP_CAP_512M) { |
| 91 | MCHBAR32(CxDTAEW(x)) = 0x20081808; |
| 92 | MCHBAR32(CxDTAEW(x)+4) = 0x3f23221b; |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | /* also L-Shaped */ |
| 97 | if (sysinfo->selected_timings.channel_mode == |
| 98 | CHANNEL_MODE_DUAL_INTERLEAVED) { |
| 99 | if (freq == MEM_CLOCK_1067MT) { |
| 100 | MCHBAR32(CxGTEW(x)) = 0xc8f81717; |
| 101 | } else |
| 102 | if (freq == MEM_CLOCK_800MT) { |
| 103 | MCHBAR32(CxGTEW(x)) = 0x96ba1717; |
| 104 | } else |
| 105 | if (freq == MEM_CLOCK_667MT) { |
| 106 | MCHBAR32(CxGTEW(x)) = 0x7d9b1717; |
| 107 | } |
| 108 | } else { |
| 109 | if (freq == MEM_CLOCK_1067MT) { |
| 110 | MCHBAR32(CxGTEW(x)) = 0x53661717; |
| 111 | } else |
| 112 | if (freq == MEM_CLOCK_800MT) { |
| 113 | MCHBAR32(CxGTEW(x)) = 0x886e1717; |
| 114 | } else |
| 115 | if (freq == MEM_CLOCK_667MT) { |
| 116 | MCHBAR32(CxGTEW(x)) = 0x38621717; |
| 117 | } |
| 118 | } |
| 119 | } |
| 120 | |
| 121 | // always? |
| 122 | MCHBAR32(CxDTC(0)) = 0x00004020; |
| 123 | MCHBAR32(CxDTC(1)) = 0x00004020; |
| 124 | MCHBAR32(CxGTC(0)) = 0x00304848; |
| 125 | MCHBAR32(CxGTC(1)) = 0x00304848; |
| 126 | |
| 127 | /* enable thermal sensors */ |
| 128 | u32 tmp; |
| 129 | tmp = MCHBAR32(0x1290) & 0xfff8; |
| 130 | MCHBAR32(0x1290) = tmp | 0xa4810007; |
| 131 | tmp = MCHBAR32(0x1390) & 0xfff8; |
| 132 | MCHBAR32(0x1390) = tmp | 0xa4810007; |
| 133 | tmp = MCHBAR32(0x12b4) & 0xfff8; |
| 134 | MCHBAR32(0x12b4) = tmp | 0xa2810007; |
| 135 | tmp = MCHBAR32(0x13b4) & 0xfff8; |
| 136 | MCHBAR32(0x13b4) = tmp | 0xa2810007; |
| 137 | MCHBAR8(0x1070) = 1; |
| 138 | MCHBAR8(0x1080) = 6; |
| 139 | if (sysinfo->gfx_type == GMCH_PM45) { |
| 140 | MCHBAR16(0x1001) = 0; |
| 141 | MCHBAR8(0x1007) = 0; |
| 142 | MCHBAR32(0x1010) = 0; |
| 143 | MCHBAR32(0x1014) = 0; |
| 144 | MCHBAR8(0x101c) = 0x98; |
| 145 | MCHBAR16(0x1041) = 0x9200; |
| 146 | MCHBAR8(0x1047) = 0; |
| 147 | MCHBAR32(0x1050) = 0x2309; |
| 148 | MCHBAR32(0x1054) = 0; |
| 149 | MCHBAR8(0x105c) = 0x98; |
| 150 | } else { |
| 151 | MCHBAR16(0x1001) = 0x9200; |
| 152 | MCHBAR8(0x1007) = 0; |
| 153 | MCHBAR32(0x1010) = 0x2309; |
| 154 | MCHBAR32(0x1014) = 0; |
| 155 | MCHBAR8(0x101c) = 0x98; |
| 156 | MCHBAR16(0x1041) = 0; |
| 157 | MCHBAR8(0x1047) = 0; |
| 158 | MCHBAR32(0x1050) = 0; |
| 159 | MCHBAR32(0x1054) = 0; |
| 160 | MCHBAR8(0x105c) = 0x98; |
| 161 | } |
| 162 | |
| 163 | MCHBAR32(0x1010) |= 1 << 31; |
| 164 | MCHBAR32(0x1050) |= 1 << 31; |
| 165 | MCHBAR32(CxGTC(0)) |= 1 << 31; |
| 166 | MCHBAR32(CxGTC(1)) |= 1 << 31; |
| 167 | |
| 168 | if (sysinfo->gs45_low_power_mode) { |
| 169 | MCHBAR32(0x11b0) = 0xa000083a; |
| 170 | } else if (sysinfo->gfx_type == GMCH_GM49) { |
| 171 | MCHBAR32(0x11b0) = 0x2000383a; |
| 172 | MCHBAR16(0x1190) &= ~(1 << 15); |
| 173 | } else if ((sysinfo->gfx_type != GMCH_PM45) && |
| 174 | (sysinfo->gfx_type != GMCH_UNKNOWN)) { |
| 175 | MCHBAR32(0x11b0) = 0xa000383a; |
| 176 | } |
| 177 | |
| 178 | switch (sysinfo->selected_timings.fsb_clock) { |
| 179 | case FSB_CLOCK_667MHz: |
| 180 | MCHBAR32(0x11d0) = 0x0fd88000; |
| 181 | break; |
| 182 | case FSB_CLOCK_800MHz: |
| 183 | MCHBAR32(0x11d0) = 0x1303c000; |
| 184 | break; |
| 185 | case FSB_CLOCK_1067MHz: |
| 186 | MCHBAR32(0x11d0) = 0x194a0000; |
| 187 | break; |
| 188 | } |
| 189 | tmp = MCHBAR32(0x11d4) & ~0x1f; |
| 190 | MCHBAR32(0x11d4) = tmp | 4; |
| 191 | } |