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Furquan Shaikh903472c2017-12-04 17:41:44 -08001chip soc/intel/skylake
2
3 # Deep Sx states
4 register "deep_s3_enable_ac" = "0"
5 register "deep_s3_enable_dc" = "1"
6 register "deep_s5_enable_ac" = "1"
7 register "deep_s5_enable_dc" = "1"
Furquan Shaikh9076b7b2018-02-05 12:08:57 -08008 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
Furquan Shaikh903472c2017-12-04 17:41:44 -08009
10 # GPE configuration
11 # Note that GPE events called out in ASL code rely on this
12 # route. i.e. If this route changes then the affected GPE
13 # offset bits also need to be changed.
14 register "gpe0_dw0" = "GPP_B"
15 register "gpe0_dw1" = "GPP_D"
16 register "gpe0_dw2" = "GPP_E"
17
18 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
19 register "gen1_dec" = "0x00fc0801"
20 register "gen2_dec" = "0x000c0201"
21 # EC memory map range is 0x900-0x9ff
22 register "gen3_dec" = "0x00fc0901"
23
Frank Wu2a67c372018-03-30 14:24:05 +080024 # Enable DPTF
25 register "dptf_enable" = "1"
26
Furquan Shaikh903472c2017-12-04 17:41:44 -080027 # Enable S0ix
28 register "s0ix_enable" = "1"
29
30 # FSP Configuration
31 register "ProbelessTrace" = "0"
32 register "EnableLan" = "0"
Kane Chencb8123a2018-01-22 16:24:10 +080033 register "EnableSata" = "0"
34 register "SataSalpSupport" = "0"
Furquan Shaikhac9fd162017-12-17 03:19:18 -080035 register "SataMode" = "0"
Furquan Shaikh903472c2017-12-04 17:41:44 -080036 register "EnableAzalia" = "1"
37 register "DspEnable" = "1"
38 register "IoBufferOwnership" = "3"
39 register "EnableTraceHub" = "0"
Furquan Shaikh903472c2017-12-04 17:41:44 -080040 register "SsicPortEnable" = "0"
41 register "SmbusEnable" = "1"
42 register "Cio2Enable" = "0"
43 register "SaImguEnable" = "0"
44 register "ScsEmmcEnabled" = "1"
45 register "ScsEmmcHs400Enabled" = "1"
46 register "ScsSdCardEnabled" = "0"
47 register "IshEnable" = "0"
48 register "PttSwitch" = "0"
49 register "InternalGfx" = "1"
50 register "SkipExtGfxScan" = "1"
51 register "Device4Enable" = "1"
52 register "HeciEnabled" = "0"
53 register "FspSkipMpInit" = "1"
54 register "SaGv" = "3"
55 register "SerialIrqConfigSirqEnable" = "1"
56 register "PmConfigSlpS3MinAssert" = "2" # 50ms
57 register "PmConfigSlpS4MinAssert" = "1" # 1s
58 register "PmConfigSlpSusMinAssert" = "1" # 500ms
59 register "PmConfigSlpAMinAssert" = "3" # 2s
60 register "PmTimerDisabled" = "1"
Furquan Shaikh92263852018-04-16 23:26:55 -070061 register "VmxEnable" = "1"
Furquan Shaikh903472c2017-12-04 17:41:44 -080062
63 register "pirqa_routing" = "PCH_IRQ11"
64 register "pirqb_routing" = "PCH_IRQ10"
65 register "pirqc_routing" = "PCH_IRQ11"
66 register "pirqd_routing" = "PCH_IRQ11"
67 register "pirqe_routing" = "PCH_IRQ11"
68 register "pirqf_routing" = "PCH_IRQ11"
69 register "pirqg_routing" = "PCH_IRQ11"
70 register "pirqh_routing" = "PCH_IRQ11"
71
72 # VR Settings Configuration for 4 Domains
73 #+----------------+-------+-------+-------+-------+
74 #| Domain/Setting | SA | IA | GTUS | GTS |
75 #+----------------+-------+-------+-------+-------+
76 #| Psi1Threshold | 20A | 20A | 20A | 20A |
77 #| Psi2Threshold | 2A | 2A | 2A | 2A |
78 #| Psi3Threshold | 1A | 1A | 1A | 1A |
79 #| Psi3Enable | 1 | 1 | 1 | 1 |
80 #| Psi4Enable | 1 | 1 | 1 | 1 |
81 #| ImonSlope | 0 | 0 | 0 | 0 |
82 #| ImonOffset | 0 | 0 | 0 | 0 |
Furquan Shaikh903472c2017-12-04 17:41:44 -080083 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
Gaggery Tsai2a81fed2018-02-05 13:47:39 +080084 #| AcLoadline | 11 | 2.4 | 3.1 | 3.1 |
85 #| DcLoadline | 10 | 2.46 | 3.1 | 3.1 |
Furquan Shaikh903472c2017-12-04 17:41:44 -080086 #+----------------+-------+-------+-------+-------+
87 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
88 .vr_config_enable = 1,
89 .psi1threshold = VR_CFG_AMP(20),
90 .psi2threshold = VR_CFG_AMP(2),
91 .psi3threshold = VR_CFG_AMP(1),
92 .psi3enable = 1,
93 .psi4enable = 1,
94 .imon_slope = 0x0,
95 .imon_offset = 0x0,
Furquan Shaikh903472c2017-12-04 17:41:44 -080096 .voltage_limit = 1520,
Gaggery Tsai2a81fed2018-02-05 13:47:39 +080097 .ac_loadline = 1100,
98 .dc_loadline = 1000,
Furquan Shaikh903472c2017-12-04 17:41:44 -080099 }"
100
101 register "domain_vr_config[VR_IA_CORE]" = "{
102 .vr_config_enable = 1,
103 .psi1threshold = VR_CFG_AMP(20),
104 .psi2threshold = VR_CFG_AMP(2),
105 .psi3threshold = VR_CFG_AMP(1),
106 .psi3enable = 1,
107 .psi4enable = 1,
108 .imon_slope = 0x0,
109 .imon_offset = 0x0,
Furquan Shaikh903472c2017-12-04 17:41:44 -0800110 .voltage_limit = 1520,
Gaggery Tsai2a81fed2018-02-05 13:47:39 +0800111 .ac_loadline = 240,
112 .dc_loadline = 246,
Furquan Shaikh903472c2017-12-04 17:41:44 -0800113 }"
114
115 register "domain_vr_config[VR_GT_UNSLICED]" = "{
116 .vr_config_enable = 1,
117 .psi1threshold = VR_CFG_AMP(20),
118 .psi2threshold = VR_CFG_AMP(2),
119 .psi3threshold = VR_CFG_AMP(1),
120 .psi3enable = 1,
121 .psi4enable = 1,
122 .imon_slope = 0x0,
123 .imon_offset = 0x0,
Furquan Shaikh903472c2017-12-04 17:41:44 -0800124 .voltage_limit = 1520,
Gaggery Tsai2a81fed2018-02-05 13:47:39 +0800125 .ac_loadline = 310,
126 .dc_loadline = 310,
Furquan Shaikh903472c2017-12-04 17:41:44 -0800127 }"
128
129 register "domain_vr_config[VR_GT_SLICED]" = "{
130 .vr_config_enable = 1,
131 .psi1threshold = VR_CFG_AMP(20),
132 .psi2threshold = VR_CFG_AMP(2),
133 .psi3threshold = VR_CFG_AMP(1),
134 .psi3enable = 1,
135 .psi4enable = 1,
136 .imon_slope = 0x0,
137 .imon_offset = 0x0,
Furquan Shaikh903472c2017-12-04 17:41:44 -0800138 .voltage_limit = 1520,
Gaggery Tsai2a81fed2018-02-05 13:47:39 +0800139 .ac_loadline = 310,
140 .dc_loadline = 310,
Furquan Shaikh903472c2017-12-04 17:41:44 -0800141 }"
142
143 # Root port 4 (x1)
144 # PcieRpEnable: Enable root port
145 # PcieRpClkReqSupport: Enable CLKREQ#
146 # PcieRpClkReqNumber: Uses SRCCLKREQ1#
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530147 # PcieRpClkSrcNumber: Uses 1
Furquan Shaikh903472c2017-12-04 17:41:44 -0800148 # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
149 # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
150 register "PcieRpEnable[3]" = "1"
151 register "PcieRpClkReqSupport[3]" = "1"
152 register "PcieRpClkReqNumber[3]" = "1"
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530153 register "PcieRpClkSrcNumber[3]" = "1"
Furquan Shaikh903472c2017-12-04 17:41:44 -0800154 register "PcieRpAdvancedErrorReporting[3]" = "1"
155 register "PcieRpLtrEnable[3]" = "1"
156
157 # Root port 5 (x4)
158 # PcieRpEnable: Enable root port
159 # PcieRpClkReqSupport: Enable CLKREQ#
160 # PcieRpClkReqNumber: Uses SRCCLKREQ3#
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530161 # PcieRpClkSrcNumber: Uses 3
Furquan Shaikh903472c2017-12-04 17:41:44 -0800162 # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
163 # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
164 register "PcieRpEnable[4]" = "1"
165 register "PcieRpClkReqSupport[4]" = "1"
166 register "PcieRpClkReqNumber[4]" = "3"
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530167 register "PcieRpClkSrcNumber[4]" = "3"
Furquan Shaikh903472c2017-12-04 17:41:44 -0800168 register "PcieRpAdvancedErrorReporting[4]" = "1"
169 register "PcieRpLtrEnable[4]" = "1"
170
171 # Root port 9 (x2)
172 # PcieRpEnable: Enable root port
173 # PcieRpClkReqSupport: Enable CLKREQ#
174 # PcieRpClkReqNumber: Uses SRCCLKREQ2#
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530175 # PcieRpClkSrcNumber: Uses 2
Furquan Shaikh903472c2017-12-04 17:41:44 -0800176 # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
177 # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
178 register "PcieRpEnable[8]" = "1"
179 register "PcieRpClkReqSupport[8]" = "1"
180 register "PcieRpClkReqNumber[8]" = "2"
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530181 register "PcieRpClkSrcNumber[8]" = "2"
Furquan Shaikh903472c2017-12-04 17:41:44 -0800182 register "PcieRpAdvancedErrorReporting[8]" = "1"
183 register "PcieRpLtrEnable[8]" = "1"
184
185 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0
186 register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1
187 register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port
188 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader
189 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WiFi
190 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Rear camera
191 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Front camera
192
193 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 0
194 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1
195 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port
196 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader
197
198 # Touchscreen
199 register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
200
201 # Trackpad
202 register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
203
204 # Pen
205 register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
206
207 # Audio
208 register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
209
210 # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
211 # communication before memory is up.
212 register "gspi[0]" = "{
213 .speed_mhz = 1,
214 .early_init = 1,
215 }"
216
217 # Must leave UART0 enabled or SD/eMMC will not work as PCI
218 register "SerialIoDevMode" = "{
219 [PchSerialIoIndexI2C0] = PchSerialIoPci,
220 [PchSerialIoIndexI2C1] = PchSerialIoPci,
221 [PchSerialIoIndexI2C2] = PchSerialIoPci,
222 [PchSerialIoIndexI2C3] = PchSerialIoPci,
223 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
224 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
225 [PchSerialIoIndexSpi0] = PchSerialIoPci,
226 [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
227 [PchSerialIoIndexUart0] = PchSerialIoPci,
228 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
229 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
230 }"
231
232 register "speed_shift_enable" = "1"
233
234 register "tcc_offset" = "10" # TCC of 90C
Gaggery Tsaicb304c12018-02-07 17:17:05 +0800235 register "psys_pmax" = "101"
Furquan Shaikh903472c2017-12-04 17:41:44 -0800236
237 # Lock Down
238 register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
239
Furquan Shaikh39d30212018-03-01 18:08:06 -0800240 # PCH Trip Temperature in degree C
241 register "pch_trip_temp" = "75"
242
Furquan Shaikh903472c2017-12-04 17:41:44 -0800243 device cpu_cluster 0 on
244 device lapic 0 on end
245 end
246 device domain 0 on
247 device pci 00.0 on end # Host Bridge
248 device pci 02.0 on end # Integrated Graphics Device
249 device pci 14.0 on end # USB xHCI
250 device pci 14.1 off end # USB xDCI (OTG)
251 device pci 14.2 on end # Thermal Subsystem
Crystal Line099b302018-02-26 17:04:06 +0800252 device pci 15.0 on
253 chip drivers/i2c/generic
254 register "hid" = ""ELAN0001""
255 register "desc" = ""ELAN Touchscreen""
256 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
257 register "probed" = "1"
258 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
259 register "reset_delay_ms" = "20"
Shelley Chen6a0eafe2018-03-14 09:55:11 -0700260 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)"
Crystal Line099b302018-02-26 17:04:06 +0800261 register "enable_delay_ms" = "1"
262 register "has_power_resource" = "1"
263 device i2c 10 on end
264 end
265 end # I2C #0
van_chenb94b2c72018-01-05 15:45:03 +0800266 device pci 15.1 on
267 chip drivers/i2c/generic
268 register "hid" = ""ELAN0000""
269 register "desc" = ""ELAN Touchpad""
270 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
Van Chenf56e71b2018-01-19 15:16:19 +0800271 register "wake" = "GPE0_DW2_16"
van_chenb94b2c72018-01-05 15:45:03 +0800272 device i2c 15 on end
273 end
ivy_jianb7641e82018-04-30 09:53:11 +0800274 chip drivers/i2c/hid
275 register "generic.hid" = ""PNP0C50""
276 register "generic.desc" = ""Synaptics Touchpad""
277 register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
278 register "generic.wake" = "GPE0_DW2_16"
279 register "generic.probed" = "1"
280 register "hid_desc_reg_offset" = "0x20"
281 device i2c 0x2c on end
282 end
van_chenb94b2c72018-01-05 15:45:03 +0800283 end # I2C #1
jasper leef393d432018-03-05 20:01:42 +0800284 device pci 15.2 on
285 chip drivers/i2c/hid
286 register "generic.hid" = ""WCOM005C""
287 register "generic.desc" = ""WCOM Digitizer""
288 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)"
289 register "generic.probed" = "1"
290 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)"
291 register "generic.reset_delay_ms" = "20"
292 register "generic.has_power_resource" = "1"
293 register "generic.disable_gpio_export_in_crs" = "1"
Shelley Chen4e0b47a2018-03-14 11:19:24 -0700294 register "generic.wake" = "GPE0_DW2_01"
jasper leef393d432018-03-05 20:01:42 +0800295 register "hid_desc_reg_offset" = "0x1"
296 device i2c 0x9 on end
297 end
Shelley Chen4e0b47a2018-03-14 11:19:24 -0700298 chip drivers/generic/gpio_keys
299 register "name" = ""PENH""
300 register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E8)"
301 register "key.dev_name" = ""EJCT""
302 register "key.linux_code" = "SW_PEN_INSERTED"
303 register "key.linux_input_type" = "EV_SW"
304 register "key.label" = ""pen_eject""
305 device generic 0 on end
306 end
jasper leef393d432018-03-05 20:01:42 +0800307 end # I2C #2
Gaggery Tsaiff9005b2017-12-13 16:47:57 +0800308 device pci 15.3 on
309 chip drivers/generic/max98357a
310 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
311 register "sdmode_delay" = "5"
312 device generic 0 on end
313 end
314 chip drivers/i2c/da7219
315 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)"
316 register "btn_cfg" = "50"
317 register "mic_det_thr" = "500"
318 register "jack_ins_deb" = "20"
319 register "jack_det_rate" = ""32ms_64ms""
320 register "jack_rem_deb" = "1"
321 register "a_d_btn_thr" = "0xa"
322 register "d_b_btn_thr" = "0x16"
323 register "b_c_btn_thr" = "0x21"
324 register "c_mic_btn_thr" = "0x3e"
325 register "btn_avg" = "4"
326 register "adc_1bit_rpt" = "1"
327 register "micbias_lvl" = "2600"
328 register "mic_amp_in_sel" = ""diff""
329 device i2c 1A on end
330 end
331 end # I2C #3
Furquan Shaikh903472c2017-12-04 17:41:44 -0800332 device pci 16.0 on end # Management Engine Interface 1
333 device pci 16.1 off end # Management Engine Interface 2
334 device pci 16.2 off end # Management Engine IDE-R
335 device pci 16.3 off end # Management Engine KT Redirection
336 device pci 16.4 off end # Management Engine Interface 3
Kane Chencb8123a2018-01-22 16:24:10 +0800337 device pci 17.0 off end # SATA
Furquan Shaikh903472c2017-12-04 17:41:44 -0800338 device pci 19.0 on end # UART #2
339 device pci 19.1 off end # I2C #5
340 device pci 19.2 off end # I2C #4
341 device pci 1c.0 on end # PCI Express Port 1
342 device pci 1c.1 off end # PCI Express Port 2
343 device pci 1c.2 off end # PCI Express Port 3
344 device pci 1c.3 on
345 chip drivers/intel/wifi
Furquan Shaikh9076b7b2018-02-05 12:08:57 -0800346 register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22
Furquan Shaikh903472c2017-12-04 17:41:44 -0800347 device pci 00.0 on end
348 end
349 end # PCI Express Port 4
350 device pci 1c.4 on end # PCI Express Port 5
351 device pci 1c.5 off end # PCI Express Port 6
352 device pci 1c.6 off end # PCI Express Port 7
353 device pci 1c.7 off end # PCI Express Port 8
354 device pci 1d.0 on end # PCI Express Port 9
355 device pci 1d.1 off end # PCI Express Port 10
356 device pci 1d.2 off end # PCI Express Port 11
357 device pci 1d.3 off end # PCI Express Port 12
358 device pci 1e.0 on end # UART #0
359 device pci 1e.1 off end # UART #1
360 device pci 1e.2 on
361 chip drivers/spi/acpi
362 register "hid" = "ACPI_DT_NAMESPACE_HID"
363 register "compat_string" = ""google,cr50""
364 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
365 device spi 0 on end
366 end
367 end # GSPI #0
368 device pci 1e.3 off end # GSPI #1
369 device pci 1e.4 on end # eMMC
370 device pci 1e.5 off end # SDIO
371 device pci 1e.6 off end # SDCard
372 device pci 1f.0 on
373 chip ec/google/chromeec
374 device pnp 0c09.0 on end
375 end
376 end # LPC Interface
377 device pci 1f.1 on end # P2SB
378 device pci 1f.2 on end # Power Management Controller
379 device pci 1f.3 on end # Intel HDA
380 device pci 1f.4 on end # SMBus
381 device pci 1f.5 on end # PCH SPI
382 device pci 1f.6 off end # GbE
383 end
384end