Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef REG_SCRIPT_H |
| 21 | #define REG_SCRIPT_H |
| 22 | |
| 23 | #include <stdint.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/resource.h> |
| 27 | |
| 28 | /* |
| 29 | * The reg script library is a way to provide data-driven I/O accesses for |
| 30 | * initializing devices. It currently supports PCI, legacy I/O, |
| 31 | * memory-mapped I/O, and IOSF accesses. |
| 32 | * |
| 33 | * In order to simplify things for the developer the following features |
| 34 | * are employed: |
| 35 | * - Chaining of tables that allow runtime tables to chain to compile-time |
| 36 | * tables. |
| 37 | * - Notion of current device (device_t) being worked on. This allows for |
| 38 | * PCI config, io, and mmio on a particular device's resources. |
| 39 | * |
| 40 | * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push |
| 41 | * and pop of the context. A chained reg_script inherits the previous |
| 42 | * context (such as current device), but it does not impact the previous |
| 43 | * context in any way. |
| 44 | */ |
| 45 | |
| 46 | enum { |
| 47 | REG_SCRIPT_COMMAND_READ, |
| 48 | REG_SCRIPT_COMMAND_WRITE, |
| 49 | REG_SCRIPT_COMMAND_RMW, |
| 50 | REG_SCRIPT_COMMAND_POLL, |
| 51 | REG_SCRIPT_COMMAND_SET_DEV, |
| 52 | REG_SCRIPT_COMMAND_NEXT, |
| 53 | REG_SCRIPT_COMMAND_END, |
| 54 | }; |
| 55 | |
| 56 | enum { |
| 57 | REG_SCRIPT_TYPE_PCI, |
| 58 | REG_SCRIPT_TYPE_IO, |
| 59 | REG_SCRIPT_TYPE_MMIO, |
| 60 | REG_SCRIPT_TYPE_RES, |
| 61 | REG_SCRIPT_TYPE_IOSF, |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 62 | REG_SCRIPT_TYPE_MSR, |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | enum { |
| 66 | REG_SCRIPT_SIZE_8, |
| 67 | REG_SCRIPT_SIZE_16, |
| 68 | REG_SCRIPT_SIZE_32, |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 69 | REG_SCRIPT_SIZE_64, |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | struct reg_script { |
| 73 | uint32_t command; |
| 74 | uint32_t type; |
| 75 | uint32_t size; |
| 76 | uint32_t reg; |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 77 | uint64_t mask; |
| 78 | uint64_t value; |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 79 | uint32_t timeout; |
| 80 | union { |
| 81 | uint32_t id; |
| 82 | const struct reg_script *next; |
| 83 | device_t dev; |
| 84 | unsigned int res_index; |
| 85 | }; |
| 86 | }; |
| 87 | |
| 88 | /* Internal helper Macros. */ |
| 89 | |
| 90 | #define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \ |
| 91 | mask_, value_, timeout_, id_) \ |
| 92 | { .command = cmd_, \ |
| 93 | .type = type_, \ |
| 94 | .size = size_, \ |
| 95 | .reg = reg_, \ |
| 96 | .mask = mask_, \ |
| 97 | .value = value_, \ |
| 98 | .timeout = timeout_, \ |
| 99 | .id = id_, \ |
| 100 | } |
| 101 | |
| 102 | #define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \ |
| 103 | mask_, value_, timeout_) \ |
| 104 | { .command = cmd_, \ |
| 105 | .type = type_, \ |
| 106 | .size = size_, \ |
| 107 | .reg = reg_, \ |
| 108 | .mask = mask_, \ |
| 109 | .value = value_, \ |
| 110 | .timeout = timeout_, \ |
| 111 | .res_index = res_index_, \ |
| 112 | } |
| 113 | |
| 114 | /* |
| 115 | * PCI |
| 116 | */ |
| 117 | |
| 118 | #define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \ |
| 119 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 120 | REG_SCRIPT_TYPE_PCI, \ |
| 121 | REG_SCRIPT_SIZE_##bits_, \ |
| 122 | reg_, mask_, value_, timeout_, 0) |
| 123 | #define REG_PCI_READ8(reg_) \ |
| 124 | REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0) |
| 125 | #define REG_PCI_READ16(reg_) \ |
| 126 | REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0) |
| 127 | #define REG_PCI_READ32(reg_) \ |
| 128 | REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0) |
| 129 | #define REG_PCI_WRITE8(reg_, value_) \ |
| 130 | REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0) |
| 131 | #define REG_PCI_WRITE16(reg_, value_) \ |
| 132 | REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0) |
| 133 | #define REG_PCI_WRITE32(reg_, value_) \ |
| 134 | REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0) |
| 135 | #define REG_PCI_RMW8(reg_, mask_, value_) \ |
| 136 | REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0) |
| 137 | #define REG_PCI_RMW16(reg_, mask_, value_) \ |
| 138 | REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0) |
| 139 | #define REG_PCI_RMW32(reg_, mask_, value_) \ |
| 140 | REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0) |
| 141 | #define REG_PCI_OR8(reg_, value_) \ |
| 142 | REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0) |
| 143 | #define REG_PCI_OR16(reg_, value_) \ |
| 144 | REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0) |
| 145 | #define REG_PCI_OR32(reg_, value_) \ |
| 146 | REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0) |
| 147 | #define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \ |
| 148 | REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_) |
| 149 | #define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \ |
| 150 | REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_) |
| 151 | #define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \ |
| 152 | REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_) |
| 153 | |
| 154 | /* |
| 155 | * Legacy IO |
| 156 | */ |
| 157 | |
| 158 | #define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \ |
| 159 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 160 | REG_SCRIPT_TYPE_IO, \ |
| 161 | REG_SCRIPT_SIZE_##bits_, \ |
| 162 | reg_, mask_, value_, timeout_, 0) |
| 163 | #define REG_IO_READ8(reg_) \ |
| 164 | REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0) |
| 165 | #define REG_IO_READ16(reg_) \ |
| 166 | REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0) |
| 167 | #define REG_IO_READ32(reg_) \ |
| 168 | REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0) |
| 169 | #define REG_IO_WRITE8(reg_, value_) \ |
| 170 | REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0) |
| 171 | #define REG_IO_WRITE16(reg_, value_) \ |
| 172 | REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0) |
| 173 | #define REG_IO_WRITE32(reg_, value_) \ |
| 174 | REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0) |
| 175 | #define REG_IO_RMW8(reg_, mask_, value_) \ |
| 176 | REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0) |
| 177 | #define REG_IO_RMW16(reg_, mask_, value_) \ |
| 178 | REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0) |
| 179 | #define REG_IO_RMW32(reg_, mask_, value_) \ |
| 180 | REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0) |
| 181 | #define REG_IO_OR8(reg_, value_) \ |
Duncan Laurie | 21fd2f4 | 2014-04-22 11:14:12 -0700 | [diff] [blame] | 182 | REG_IO_RMW8(reg_, 0xff, value_) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 183 | #define REG_IO_OR16(reg_, value_) \ |
Duncan Laurie | 21fd2f4 | 2014-04-22 11:14:12 -0700 | [diff] [blame] | 184 | REG_IO_RMW16(reg_, 0xffff, value_) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 185 | #define REG_IO_OR32(reg_, value_) \ |
Duncan Laurie | 21fd2f4 | 2014-04-22 11:14:12 -0700 | [diff] [blame] | 186 | REG_IO_RMW32(reg_, 0xffffffff, value_) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 187 | #define REG_IO_POLL8(reg_, mask_, value_, timeout_) \ |
| 188 | REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_) |
| 189 | #define REG_IO_POLL16(reg_, mask_, value_, timeout_) \ |
| 190 | REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_) |
| 191 | #define REG_IO_POLL32(reg_, mask_, value_, timeout_) \ |
| 192 | REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_) |
| 193 | |
| 194 | /* |
| 195 | * Memory Mapped IO |
| 196 | */ |
| 197 | |
| 198 | #define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \ |
| 199 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 200 | REG_SCRIPT_TYPE_MMIO, \ |
| 201 | REG_SCRIPT_SIZE_##bits_, \ |
| 202 | reg_, mask_, value_, timeout_, 0) |
| 203 | #define REG_MMIO_READ8(reg_) \ |
| 204 | REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0) |
| 205 | #define REG_MMIO_READ16(reg_) \ |
| 206 | REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0) |
| 207 | #define REG_MMIO_READ32(reg_) \ |
| 208 | REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0) |
| 209 | #define REG_MMIO_WRITE8(reg_, value_) \ |
| 210 | REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0) |
| 211 | #define REG_MMIO_WRITE16(reg_, value_) \ |
| 212 | REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0) |
| 213 | #define REG_MMIO_WRITE32(reg_, value_) \ |
| 214 | REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0) |
| 215 | #define REG_MMIO_RMW8(reg_, mask_, value_) \ |
| 216 | REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0) |
| 217 | #define REG_MMIO_RMW16(reg_, mask_, value_) \ |
| 218 | REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0) |
| 219 | #define REG_MMIO_RMW32(reg_, mask_, value_) \ |
| 220 | REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0) |
| 221 | #define REG_MMIO_OR8(reg_, value_) \ |
| 222 | REG_MMIO_RMW8(reg_, 0xff, value_) |
| 223 | #define REG_MMIO_OR16(reg_, value_) \ |
| 224 | REG_MMIO_RMW16(reg_, 0xffff, value_) |
| 225 | #define REG_MMIO_OR32(reg_, value_) \ |
| 226 | REG_MMIO_RMW32(reg_, 0xffffffff, value_) |
| 227 | #define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \ |
| 228 | REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_) |
| 229 | #define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \ |
| 230 | REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_) |
| 231 | #define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \ |
| 232 | REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_) |
| 233 | |
| 234 | /* |
| 235 | * Access through a device's resource such as a Base Address Register (BAR) |
| 236 | */ |
| 237 | |
| 238 | #define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \ |
| 239 | _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \ |
| 240 | REG_SCRIPT_TYPE_RES, bar_, \ |
| 241 | REG_SCRIPT_SIZE_##bits_, \ |
| 242 | reg_, mask_, value_, timeout_) |
| 243 | #define REG_RES_READ8(bar_, reg_) \ |
| 244 | REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0) |
| 245 | #define REG_RES_READ16(bar_, reg_) \ |
| 246 | REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0) |
| 247 | #define REG_RES_READ32(bar_, reg_) \ |
| 248 | REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0) |
| 249 | #define REG_RES_WRITE8(bar_, reg_, value_) \ |
| 250 | REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0) |
| 251 | #define REG_RES_WRITE16(bar_, reg_, value_) \ |
| 252 | REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0) |
| 253 | #define REG_RES_WRITE32(bar_, reg_, value_) \ |
| 254 | REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0) |
| 255 | #define REG_RES_RMW8(bar_, reg_, mask_, value_) \ |
| 256 | REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0) |
| 257 | #define REG_RES_RMW16(bar_, reg_, mask_, value_) \ |
| 258 | REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0) |
| 259 | #define REG_RES_RMW32(bar_, reg_, mask_, value_) \ |
| 260 | REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0) |
| 261 | #define REG_RES_OR8(bar_, reg_, value_) \ |
| 262 | REG_RES_RMW8(bar_, reg_, 0xff, value_) |
| 263 | #define REG_RES_OR16(bar_, reg_, value_) \ |
| 264 | REG_RES_RMW16(bar_, reg_, 0xffff, value_) |
| 265 | #define REG_RES_OR32(bar_, reg_, value_) \ |
| 266 | REG_RES_RMW32(bar_, reg_, 0xffffffff, value_) |
| 267 | #define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \ |
| 268 | REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_) |
| 269 | #define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \ |
| 270 | REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_) |
| 271 | #define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \ |
| 272 | REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_) |
| 273 | |
| 274 | /* |
| 275 | * IO Sideband Function |
| 276 | */ |
| 277 | |
| 278 | #define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \ |
| 279 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 280 | REG_SCRIPT_TYPE_IOSF, \ |
| 281 | REG_SCRIPT_SIZE_32, \ |
| 282 | reg_, mask_, value_, timeout_, unit_) |
| 283 | #define REG_IOSF_READ(unit_, reg_) \ |
| 284 | REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0) |
| 285 | #define REG_IOSF_WRITE(unit_, reg_, value_) \ |
| 286 | REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0) |
| 287 | #define REG_IOSF_RMW(unit_, reg_, mask_, value_) \ |
| 288 | REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0) |
| 289 | #define REG_IOSF_OR(unit_, reg_, value_) \ |
| 290 | REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) |
| 291 | #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ |
| 292 | REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) |
| 293 | |
| 294 | /* |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 295 | * CPU Model Specific Register |
| 296 | */ |
| 297 | |
| 298 | #define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \ |
| 299 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 300 | REG_SCRIPT_TYPE_MSR, \ |
| 301 | REG_SCRIPT_SIZE_64, \ |
| 302 | reg_, mask_, value_, timeout_, 0) |
| 303 | #define REG_MSR_READ(reg_) \ |
| 304 | REG_SCRIPT_MSR(READ, reg_, 0, 0, 0) |
| 305 | #define REG_MSR_WRITE(reg_, value_) \ |
| 306 | REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0) |
| 307 | #define REG_MSR_RMW(reg_, mask_, value_) \ |
| 308 | REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0) |
| 309 | #define REG_MSR_OR(reg_, value_) \ |
| 310 | REG_MSR_RMW(reg_, -1ULL, value_) |
| 311 | #define REG_MSR_POLL(reg_, mask_, value_, timeout_) \ |
| 312 | REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_) |
| 313 | |
| 314 | /* |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 315 | * Chain to another table. |
| 316 | */ |
| 317 | #define REG_SCRIPT_NEXT(next_) \ |
| 318 | { .command = REG_SCRIPT_COMMAND_NEXT, \ |
| 319 | .next = next_, \ |
| 320 | } |
| 321 | |
| 322 | /* |
| 323 | * Set current device |
| 324 | */ |
| 325 | #define REG_SCRIPT_SET_DEV(dev_) \ |
| 326 | { .command = REG_SCRIPT_COMMAND_SET_DEV, \ |
| 327 | .dev = dev_, \ |
| 328 | } |
| 329 | |
| 330 | /* |
| 331 | * Last script entry. All tables need to end with REG_SCRIPT_END. |
| 332 | */ |
| 333 | #define REG_SCRIPT_END \ |
| 334 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) |
| 335 | |
| 336 | void reg_script_run(const struct reg_script *script); |
Aaron Durbin | d86f0b7 | 2013-12-10 17:09:40 -0800 | [diff] [blame] | 337 | void reg_script_run_on_dev(device_t dev, const struct reg_script *step); |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 338 | |
| 339 | #endif /* REG_SCRIPT_H */ |