blob: f17a44ff178bf1a78f2eb0768af828f9da77bb90 [file] [log] [blame]
Martin Rothbf6b83a2015-10-11 10:37:02 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Martin Rothbf6b83a2015-10-11 10:37:02 +020016 */
17
18#include <console/console.h>
19#include <device/device.h>
20#include <device/pci.h>
21#include <device/pci_ids.h>
22#include <pc80/mc146818rtc.h>
23#include <pc80/isa-dma.h>
24#include <pc80/i8259.h>
25#include <arch/io.h>
26#include <arch/ioapic.h>
27#include <arch/acpi.h>
28#include <cpu/cpu.h>
29#include <elog.h>
30#include <arch/acpigen.h>
31#include <drivers/intel/gma/i915.h>
32#include <cpu/x86/smm.h>
33#include <cbmem.h>
34#include <string.h>
35#include "pch.h"
36#include "nvs.h"
37
38#define NMI_OFF 0
39
40#define ENABLE_ACPI_MODE_IN_COREBOOT 0
41
42typedef struct southbridge_intel_fsp_bd82x6x_config config_t;
43
44static void pch_enable_apic(struct device *dev)
45{
46 int i;
47 u32 reg32;
48 volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
49 volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
50
51 /* Enable ACPI I/O and power management.
52 * Set SCI IRQ to IRQ9
53 */
54 pci_write_config8(dev, ACPI_CNTL, 0x80);
55
56 *ioapic_index = 0;
57 *ioapic_data = (1 << 25);
58
59 /* affirm full set of redirection table entries ("write once") */
60 *ioapic_index = 1;
61 reg32 = *ioapic_data;
62 *ioapic_index = 1;
63 *ioapic_data = reg32;
64
65 *ioapic_index = 0;
66 reg32 = *ioapic_data;
67 printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
68 if (reg32 != (1 << 25))
69 die("APIC Error\n");
70
71 printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
72 for (i=0; i<3; i++) {
73 *ioapic_index = i;
74 printk(BIOS_SPEW, " reg 0x%04x:", i);
75 reg32 = *ioapic_data;
76 printk(BIOS_SPEW, " 0x%08x\n", reg32);
77 }
78
79 *ioapic_index = 3; /* Select Boot Configuration register. */
80 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
81}
82
83static void pch_enable_serial_irqs(struct device *dev)
84{
85 /* Set packet length and toggle silent mode bit for one frame. */
86 pci_write_config8(dev, SERIRQ_CNTL,
87 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
Martin Roth7a1a3ad2017-06-24 21:29:38 -060088#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
Martin Rothbf6b83a2015-10-11 10:37:02 +020089 pci_write_config8(dev, SERIRQ_CNTL,
90 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
91#endif
92}
93
94/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
95 * 0x00 - 0000 = Reserved
96 * 0x01 - 0001 = Reserved
97 * 0x02 - 0010 = Reserved
98 * 0x03 - 0011 = IRQ3
99 * 0x04 - 0100 = IRQ4
100 * 0x05 - 0101 = IRQ5
101 * 0x06 - 0110 = IRQ6
102 * 0x07 - 0111 = IRQ7
103 * 0x08 - 1000 = Reserved
104 * 0x09 - 1001 = IRQ9
105 * 0x0A - 1010 = IRQ10
106 * 0x0B - 1011 = IRQ11
107 * 0x0C - 1100 = IRQ12
108 * 0x0D - 1101 = Reserved
109 * 0x0E - 1110 = IRQ14
110 * 0x0F - 1111 = IRQ15
111 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
112 * 0x80 - The PIRQ is not routed.
113 */
114
115static void pch_pirq_init(device_t dev)
116{
117 device_t irq_dev;
118 /* Get the chip configuration */
119 config_t *config = dev->chip_info;
120
121 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
122 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
123 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
124 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
125
126 pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
127 pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
128 pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
129 pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
130
131 /* Eric Biederman once said we should let the OS do this.
132 * I am not so sure anymore he was right.
133 */
134
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200135 for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
Martin Rothbf6b83a2015-10-11 10:37:02 +0200136 u8 int_pin=0, int_line=0;
137
138 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
139 continue;
140
141 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
142
143 switch (int_pin) {
144 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
145 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
146 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
147 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
148 }
149
150 if (!int_line)
151 continue;
152
153 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
154 }
155}
156
157static void pch_gpi_routing(device_t dev)
158{
159 /* Get the chip configuration */
160 config_t *config = dev->chip_info;
161 u32 reg32 = 0;
162
163 /* An array would be much nicer here, or some
164 * other method of doing this.
165 */
166 reg32 |= (config->gpi0_routing & 0x03) << 0;
167 reg32 |= (config->gpi1_routing & 0x03) << 2;
168 reg32 |= (config->gpi2_routing & 0x03) << 4;
169 reg32 |= (config->gpi3_routing & 0x03) << 6;
170 reg32 |= (config->gpi4_routing & 0x03) << 8;
171 reg32 |= (config->gpi5_routing & 0x03) << 10;
172 reg32 |= (config->gpi6_routing & 0x03) << 12;
173 reg32 |= (config->gpi7_routing & 0x03) << 14;
174 reg32 |= (config->gpi8_routing & 0x03) << 16;
175 reg32 |= (config->gpi9_routing & 0x03) << 18;
176 reg32 |= (config->gpi10_routing & 0x03) << 20;
177 reg32 |= (config->gpi11_routing & 0x03) << 22;
178 reg32 |= (config->gpi12_routing & 0x03) << 24;
179 reg32 |= (config->gpi13_routing & 0x03) << 26;
180 reg32 |= (config->gpi14_routing & 0x03) << 28;
181 reg32 |= (config->gpi15_routing & 0x03) << 30;
182
183 pci_write_config32(dev, GPIO_ROUT, reg32);
184}
185
186static void pch_power_options(device_t dev)
187{
188 u8 reg8;
189 u16 reg16, pmbase;
190 u32 reg32;
191 const char *state;
192 /* Get the chip configuration */
193 config_t *config = dev->chip_info;
194
195 int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
196 int nmi_option;
197
198 /* Which state do we want to goto after g3 (power restored)?
199 * 0 == S0 Full On
200 * 1 == S5 Soft Off
201 *
202 * If the option is not existent (Laptops), use Kconfig setting.
203 */
204 get_option(&pwr_on, "power_on_after_fail");
205
206 reg16 = pci_read_config16(dev, GEN_PMCON_3);
207 reg16 &= 0xfffe;
208 switch (pwr_on) {
209 case MAINBOARD_POWER_OFF:
210 reg16 |= 1;
211 state = "off";
212 break;
213 case MAINBOARD_POWER_ON:
214 reg16 &= ~1;
215 state = "on";
216 break;
217 case MAINBOARD_POWER_KEEP:
218 reg16 &= ~1;
219 state = "state keep";
220 break;
221 default:
222 state = "undefined";
223 }
224
225 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
226 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
227
228 reg16 &= ~(1 << 10);
229 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
230
231 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
232
233 pci_write_config16(dev, GEN_PMCON_3, reg16);
234 printk(BIOS_INFO, "Set power %s after power failure.\n", state);
235
236 /* Set up NMI on errors. */
237 reg8 = inb(0x61);
238 reg8 &= 0x0f; /* Higher Nibble must be 0 */
239 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
240 // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
241 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
242 outb(reg8, 0x61);
243
244 reg8 = inb(0x70);
245 nmi_option = NMI_OFF;
246 get_option(&nmi_option, "nmi");
247 if (nmi_option) {
248 printk(BIOS_INFO, "NMI sources enabled.\n");
249 reg8 &= ~(1 << 7); /* Set NMI. */
250 } else {
251 printk(BIOS_INFO, "NMI sources disabled.\n");
Elyes HAOUAS9c5d4632018-04-26 22:21:21 +0200252 reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
Martin Rothbf6b83a2015-10-11 10:37:02 +0200253 }
254 outb(reg8, 0x70);
255
256 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
257 reg16 = pci_read_config16(dev, GEN_PMCON_1);
258 reg16 &= ~(3 << 0); // SMI# rate 1 minute
259 reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME
260#if DEBUG_PERIODIC_SMIS
261 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
262 * periodic SMIs.
263 */
264 reg16 |= (3 << 0); // Periodic SMI every 8s
265#endif
266 pci_write_config16(dev, GEN_PMCON_1, reg16);
267
268 // Set the board's GPI routing.
269 pch_gpi_routing(dev);
270
271 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
272
273 outl(config->gpe0_en, pmbase + GPE0_EN);
274 outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
275
276 /* Set up power management block and determine sleep mode */
277 reg32 = inl(pmbase + 0x04); // PM1_CNT
278 reg32 &= ~(7 << 10); // SLP_TYP
279 reg32 |= (1 << 0); // SCI_EN
280 outl(reg32, pmbase + 0x04);
281
282 /* Clear magic status bits to prevent unexpected wake */
283 reg32 = RCBA32(0x3310);
284 reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
285 RCBA32(0x3310) = reg32;
286}
287
288static void pch_rtc_init(struct device *dev)
289{
290 u8 reg8;
291 int rtc_failed;
292
293 reg8 = pci_read_config8(dev, GEN_PMCON_3);
294 rtc_failed = reg8 & RTC_BATTERY_DEAD;
295 if (rtc_failed) {
296 reg8 &= ~RTC_BATTERY_DEAD;
297 pci_write_config8(dev, GEN_PMCON_3, reg8);
Martin Roth7a1a3ad2017-06-24 21:29:38 -0600298#if IS_ENABLED(CONFIG_ELOG)
Martin Rothbf6b83a2015-10-11 10:37:02 +0200299 elog_add_event(ELOG_TYPE_RTC_RESET);
300#endif
301 }
302 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
303
304 cmos_init(rtc_failed);
305}
306
307/* CougarPoint PCH Power Management init */
308static void cpt_pm_init(struct device *dev)
309{
310 printk(BIOS_DEBUG, "CougarPoint PM init\n");
311 pci_write_config8(dev, 0xa9, 0x47);
312 RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0));
313 RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
314 RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
315 RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
316 RCBA32(0x2304) = 0xc0388400;
317 RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
318 RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
319 RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
320 RCBA32(0x3318) = 0x050f0000;
321 RCBA32(0x3324) = 0x04000000;
322 RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
323 RCBA32_AND_OR(0x3344, ~0UL, (1 << 1));
324 RCBA32(0x3360) = 0x0001c000;
325 RCBA32(0x3368) = 0x00061100;
326 RCBA32(0x3378) = 0x7f8fdfff;
327 RCBA32(0x337c) = 0x000003fc;
328 RCBA32(0x3388) = 0x00001000;
329 RCBA32(0x3390) = 0x0001c000;
330 RCBA32(0x33a0) = 0x00000800;
331 RCBA32(0x33b0) = 0x00001000;
332 RCBA32(0x33c0) = 0x00093900;
333 RCBA32(0x33cc) = 0x24653002;
334 RCBA32(0x33d0) = 0x062108fe;
335 RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
336 RCBA32(0x3a28) = 0x01010000;
337 RCBA32(0x3a2c) = 0x01010404;
338 RCBA32(0x3a80) = 0x01041041;
339 RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
340 RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
341 RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */
342 RCBA32(0x3a6c) = 0x00000001;
343 RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
344 RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
345 RCBA32(0x33c8) = 0;
346 RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
347}
348
349/* PantherPoint PCH Power Management init */
350static void ppt_pm_init(struct device *dev)
351{
352 printk(BIOS_DEBUG, "PantherPoint PM init\n");
353 pci_write_config8(dev, 0xa9, 0x47);
354 RCBA32_AND_OR(0x2238, ~0UL, (1 << 0));
355 RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
356 RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
357 RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
358 RCBA32(0x2304) = 0xc03b8400;
359 RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
360 RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
361 RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
362 RCBA32(0x3318) = 0x054f0000;
363 RCBA32(0x3324) = 0x04000000;
364 RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
365 RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0));
366 RCBA32(0x3360) = 0x0001c000;
367 RCBA32(0x3368) = 0x00061100;
368 RCBA32(0x3378) = 0x7f8fdfff;
369 RCBA32(0x337c) = 0x000003fd;
370 RCBA32(0x3388) = 0x00001000;
371 RCBA32(0x3390) = 0x0001c000;
372 RCBA32(0x33a0) = 0x00000800;
373 RCBA32(0x33b0) = 0x00001000;
374 RCBA32(0x33c0) = 0x00093900;
375 RCBA32(0x33cc) = 0x24653002;
376 RCBA32(0x33d0) = 0x067388fe;
377 RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
378 RCBA32(0x3a28) = 0x01010000;
379 RCBA32(0x3a2c) = 0x01010404;
380 RCBA32(0x3a80) = 0x01040000;
381 RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
382 RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
383 RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */
384 RCBA32(0x3a6c) = 0x00000001;
385 RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
386 RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
387 RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0));
388 RCBA32(0x33c8) = 0;
389 RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
390}
391
392static void enable_hpet(void)
393{
394 u32 reg32;
395
396 /* Move HPET to default address 0xfed00000 and enable it */
397 reg32 = RCBA32(HPTC);
398 reg32 |= (1 << 7); // HPET Address Enable
399 reg32 &= ~(3 << 0);
400 RCBA32(HPTC) = reg32;
401}
402
403static void pch_set_acpi_mode(void)
404{
405 if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
406#if ENABLE_ACPI_MODE_IN_COREBOOT
407 printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
408 outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
409 printk(BIOS_DEBUG, "done.\n");
410#else
411 printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
412 outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
413 printk(BIOS_DEBUG, "done.\n");
414#endif
415 }
416}
417
418static void pch_disable_smm_only_flashing(struct device *dev)
419{
420 u8 reg8;
421
422 printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
423 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
424 reg8 &= ~(1 << 5);
425 pci_write_config8(dev, 0xdc, reg8);
426}
427
428static void pch_fixups(struct device *dev)
429{
430 u8 gen_pmcon_2;
431
432 /* Indicate DRAM init done for MRC S3 to know it can resume */
433 gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
434 gen_pmcon_2 |= (1 << 7);
435 pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
436
437}
438
439static void pch_decode_init(struct device *dev)
440{
441 config_t *config = dev->chip_info;
442
443 printk(BIOS_DEBUG, "pch_decode_init\n");
444
445 pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec);
446 pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec);
447 pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec);
448 pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
449}
450
451static void lpc_init(struct device *dev)
452{
453 printk(BIOS_DEBUG, "pch: lpc_init\n");
454
455 /* Set the value for PCI command register. */
456 pci_write_config16(dev, PCI_COMMAND, 0x000f);
457
458 /* IO APIC initialization. */
459 pch_enable_apic(dev);
460
461 pch_enable_serial_irqs(dev);
462
463 /* Setup the PIRQ. */
464 pch_pirq_init(dev);
465
466 /* Setup power options. */
467 pch_power_options(dev);
468
469 /* Initialize power management */
470 switch (pch_silicon_type()) {
471 case PCH_TYPE_CPT: /* CougarPoint */
472 cpt_pm_init(dev);
473 break;
474 case PCH_TYPE_PPT: /* PantherPoint */
475 ppt_pm_init(dev);
476 break;
477 default:
478 printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
479 }
480
481 /* Set the state of the GPIO lines. */
482 //gpio_init(dev);
483
484 /* Initialize the real time clock. */
485 pch_rtc_init(dev);
486
487 /* Initialize ISA DMA. */
488 isa_dma_init();
489
490 /* Initialize the High Precision Event Timers, if present. */
491 enable_hpet();
492
493 setup_i8259();
494
495 /* The OS should do this? */
496 /* Interrupt 9 should be level triggered (SCI) */
497 i8259_configure_irq_trigger(9, 1);
498
499 pch_disable_smm_only_flashing(dev);
500
501 pch_set_acpi_mode();
502
503 pch_fixups(dev);
504}
505
506static void pch_lpc_read_resources(device_t dev)
507{
508 struct resource *res;
509 config_t *config = dev->chip_info;
510 u8 io_index = 0;
511
512 /* Get the normal PCI resources of this device. */
513 pci_dev_read_resources(dev);
514
515 /* Add an extra subtractive resource for both memory and I/O. */
516 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
517 res->base = 0;
518 res->size = 0x1000;
519 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
520 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
521
522 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
523 res->base = 0xff800000;
524 res->size = 0x00800000; /* 8 MB for flash */
525 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
526 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
527
528 res = new_resource(dev, 3); /* IOAPIC */
529 res->base = IO_APIC_ADDR;
530 res->size = 0x00001000;
531 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
532
533 /* Set PCH IO decode ranges if required.*/
534 if ((config->gen1_dec & 0xFFFC) > 0x1000) {
535 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
536 res->base = config->gen1_dec & 0xFFFC;
537 res->size = (config->gen1_dec >> 16) & 0xFC;
538 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
539 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
540 }
541
542 if ((config->gen2_dec & 0xFFFC) > 0x1000) {
543 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
544 res->base = config->gen2_dec & 0xFFFC;
545 res->size = (config->gen2_dec >> 16) & 0xFC;
546 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
547 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
548 }
549
550 if ((config->gen3_dec & 0xFFFC) > 0x1000) {
551 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
552 res->base = config->gen3_dec & 0xFFFC;
553 res->size = (config->gen3_dec >> 16) & 0xFC;
554 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
555 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
556 }
557
558 if ((config->gen4_dec & 0xFFFC) > 0x1000) {
559 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
560 res->base = config->gen4_dec & 0xFFFC;
561 res->size = (config->gen4_dec >> 16) & 0xFC;
562 res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE |
563 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
564 }
565}
566
567static void pch_lpc_enable_resources(device_t dev)
568{
569 pch_decode_init(dev);
570 return pci_dev_enable_resources(dev);
571}
572
573static void pch_lpc_enable(device_t dev)
574{
575 pch_enable(dev);
576}
577
578static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
579{
580 if (!vendor || !device) {
581 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
582 pci_read_config32(dev, PCI_VENDOR_ID));
583 } else {
584 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
585 ((device & 0xffff) << 16) | (vendor & 0xffff));
586 }
587}
588
589static void southbridge_inject_dsdt(device_t dev)
590{
Elyes HAOUAS035df002016-10-03 21:54:16 +0200591 global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
Martin Rothbf6b83a2015-10-11 10:37:02 +0200592
593 if (gnvs) {
594 const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
595
Elyes HAOUAS035df002016-10-03 21:54:16 +0200596 memset(gnvs, 0, sizeof(*gnvs));
Martin Rothbf6b83a2015-10-11 10:37:02 +0200597
598 acpi_create_gnvs(gnvs);
Martin Rothbf6b83a2015-10-11 10:37:02 +0200599
600 gnvs->ndid = gfx->ndid;
601 memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
602
603 /* And tell SMI about it */
604 smm_setup_structures(gnvs, NULL, NULL);
605
606 /* Add it to DSDT. */
607 acpigen_write_scope("\\");
608 acpigen_write_name_dword("NVSA", (u32) gnvs);
609 acpigen_pop_len();
610 }
611}
612
613void acpi_fill_fadt(acpi_fadt_t *fadt)
614{
615 device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
616 config_t *chip = dev->chip_info;
617 u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
618 int c2_latency;
619
620 fadt->model = 1;
621
622 fadt->sci_int = 0x9;
623 fadt->smi_cmd = APM_CNT;
624 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
625 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
626 fadt->s4bios_req = 0x0;
627 fadt->pstate_cnt = 0;
628
629 fadt->pm1a_evt_blk = pmbase;
630 fadt->pm1b_evt_blk = 0x0;
631 fadt->pm1a_cnt_blk = pmbase + 0x4;
632 fadt->pm1b_cnt_blk = 0x0;
633 fadt->pm2_cnt_blk = pmbase + 0x50;
634 fadt->pm_tmr_blk = pmbase + 0x8;
635 fadt->gpe0_blk = pmbase + 0x20;
636 fadt->gpe1_blk = 0;
637
638 fadt->pm1_evt_len = 4;
639 fadt->pm1_cnt_len = 2;
640 fadt->pm2_cnt_len = 1;
641 fadt->pm_tmr_len = 4;
642 fadt->gpe0_blk_len = 16;
643 fadt->gpe1_blk_len = 0;
644 fadt->gpe1_base = 0;
645 fadt->cst_cnt = 0;
646 c2_latency = chip->c2_latency;
647 if (!c2_latency) {
648 c2_latency = 101; /* c2 unsupported */
649 }
650 fadt->p_lvl2_lat = c2_latency;
651 fadt->p_lvl3_lat = 87;
652 fadt->flush_size = 1024;
653 fadt->flush_stride = 16;
654 fadt->duty_offset = 1;
655 if (chip->p_cnt_throttling_supported) {
656 fadt->duty_width = 3;
657 } else {
658 fadt->duty_width = 0;
659 }
660 fadt->day_alrm = 0xd;
661 fadt->mon_alrm = 0x00;
662 fadt->century = 0x00;
663 fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
664
665 fadt->flags = ACPI_FADT_WBINVD |
666 ACPI_FADT_C1_SUPPORTED |
667 ACPI_FADT_SLEEP_BUTTON |
668 ACPI_FADT_RESET_REGISTER |
669 ACPI_FADT_SEALED_CASE |
670 ACPI_FADT_S4_RTC_WAKE |
671 ACPI_FADT_PLATFORM_CLOCK;
672 if (c2_latency < 100) {
673 fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED;
674 }
675
676 fadt->reset_reg.space_id = 1;
677 fadt->reset_reg.bit_width = 8;
678 fadt->reset_reg.bit_offset = 0;
679 fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
680 fadt->reset_reg.addrl = 0xcf9;
681 fadt->reset_reg.addrh = 0;
682
683 fadt->reset_value = 6;
684
685 fadt->x_pm1a_evt_blk.space_id = 1;
686 fadt->x_pm1a_evt_blk.bit_width = 32;
687 fadt->x_pm1a_evt_blk.bit_offset = 0;
688 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
689 fadt->x_pm1a_evt_blk.addrl = pmbase;
690 fadt->x_pm1a_evt_blk.addrh = 0x0;
691
692 fadt->x_pm1b_evt_blk.space_id = 1;
693 fadt->x_pm1b_evt_blk.bit_width = 0;
694 fadt->x_pm1b_evt_blk.bit_offset = 0;
695 fadt->x_pm1b_evt_blk.access_size = 0;
696 fadt->x_pm1b_evt_blk.addrl = 0x0;
697 fadt->x_pm1b_evt_blk.addrh = 0x0;
698
699 fadt->x_pm1a_cnt_blk.space_id = 1;
700 fadt->x_pm1a_cnt_blk.bit_width = 16;
701 fadt->x_pm1a_cnt_blk.bit_offset = 0;
702 fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
703 fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
704 fadt->x_pm1a_cnt_blk.addrh = 0x0;
705
706 fadt->x_pm1b_cnt_blk.space_id = 1;
707 fadt->x_pm1b_cnt_blk.bit_width = 0;
708 fadt->x_pm1b_cnt_blk.bit_offset = 0;
709 fadt->x_pm1b_cnt_blk.access_size = 0;
710 fadt->x_pm1b_cnt_blk.addrl = 0x0;
711 fadt->x_pm1b_cnt_blk.addrh = 0x0;
712
713 fadt->x_pm2_cnt_blk.space_id = 1;
714 fadt->x_pm2_cnt_blk.bit_width = 8;
715 fadt->x_pm2_cnt_blk.bit_offset = 0;
716 fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
717 fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
718 fadt->x_pm2_cnt_blk.addrh = 0x0;
719
720 fadt->x_pm_tmr_blk.space_id = 1;
721 fadt->x_pm_tmr_blk.bit_width = 32;
722 fadt->x_pm_tmr_blk.bit_offset = 0;
723 fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
724 fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
725 fadt->x_pm_tmr_blk.addrh = 0x0;
726
727 fadt->x_gpe0_blk.space_id = 1;
728 fadt->x_gpe0_blk.bit_width = 128;
729 fadt->x_gpe0_blk.bit_offset = 0;
730 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
731 fadt->x_gpe0_blk.addrl = pmbase + 0x20;
732 fadt->x_gpe0_blk.addrh = 0x0;
733
734 fadt->x_gpe1_blk.space_id = 1;
735 fadt->x_gpe1_blk.bit_width = 0;
736 fadt->x_gpe1_blk.bit_offset = 0;
737 fadt->x_gpe1_blk.access_size = 0;
738 fadt->x_gpe1_blk.addrl = 0x0;
739 fadt->x_gpe1_blk.addrh = 0x0;
740}
741
Bill XIEd533b162017-08-22 16:26:22 +0800742static void lpc_final(struct device *dev)
743{
744 /* Call SMM finalize() handlers before resume */
745 if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
746 if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) ||
747 acpi_is_wakeup_s3()) {
748 outb(APM_CNT_FINALIZE, APM_CNT);
749 }
750 }
751}
752
Martin Rothbf6b83a2015-10-11 10:37:02 +0200753static struct pci_operations pci_ops = {
754 .set_subsystem = set_subsystem,
755};
756
757static struct device_operations device_ops = {
758 .read_resources = pch_lpc_read_resources,
759 .set_resources = pci_dev_set_resources,
760 .enable_resources = pch_lpc_enable_resources,
761 .write_acpi_tables = acpi_write_hpet,
762 .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
763 .init = lpc_init,
Bill XIEd533b162017-08-22 16:26:22 +0800764 .final = lpc_final,
Martin Rothbf6b83a2015-10-11 10:37:02 +0200765 .enable = pch_lpc_enable,
766 .scan_bus = scan_lpc_bus,
767 .ops_pci = &pci_ops,
768};
769
770
771/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
772 * Intel C200 Series Chipset
773 */
774
775static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a,
776 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e,
777 0x1c4f, 0x1c50, 0x1c52, 0x1c54,
778 0x1e55, 0x1c56, 0x1e57, 0x1c5c,
779 0x1e5d, 0x1e5e, 0x1e5f, 0x2310,
780 0 };
781
782static const struct pci_driver pch_lpc __pci_driver = {
783 .ops = &device_ops,
784 .vendor = PCI_VENDOR_ID_INTEL,
785 .devices = pci_device_ids,
786};