Patrick Rudolph | b94ecc4 | 2019-02-22 12:05:16 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2018 Facebook, Inc. |
| 5 | * Copyright 2003-2017 Cavium Inc. <support@cavium.com> |
| 6 | * Copyright 2019 9elements Agency GmbH |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. |
| 18 | */ |
| 19 | |
Patrick Rudolph | b94ecc4 | 2019-02-22 12:05:16 +0100 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
| 21 | #include <device/pci_def.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <soc/addressmap.h> |
| 24 | #include <soc/ecam.h> |
Patrick Rudolph | b94ecc4 | 2019-02-22 12:05:16 +0100 | [diff] [blame] | 25 | |
| 26 | /** |
| 27 | * Get PCI BAR address from cavium specific extended capability. |
| 28 | * Use regular BAR if not found in extended capability space. |
| 29 | * |
| 30 | * @return The pyhsical address of the BAR, zero on error |
| 31 | */ |
| 32 | #ifdef __SIMPLE_DEVICE__ |
| 33 | uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar) |
| 34 | #else |
| 35 | uint64_t ecam0_get_bar_val(struct device *dev, u8 bar) |
| 36 | #endif |
| 37 | { |
| 38 | size_t cap_offset = pci_find_capability(dev, 0x14); |
| 39 | uint64_t h, l, ret = 0; |
| 40 | if (cap_offset) { |
| 41 | /* Found EA */ |
| 42 | u8 es, bei; |
| 43 | u8 ne = pci_read_config8(dev, cap_offset + 2) & 0x3f; |
| 44 | |
| 45 | cap_offset += 4; |
| 46 | while (ne) { |
| 47 | uint32_t dw0 = pci_read_config32(dev, cap_offset); |
| 48 | |
| 49 | es = dw0 & 7; |
| 50 | bei = (dw0 >> 4) & 0xf; |
| 51 | if (bei == bar) { |
| 52 | h = 0; |
| 53 | l = pci_read_config32(dev, cap_offset + 4); |
| 54 | if (l & 2) |
| 55 | h = pci_read_config32(dev, |
| 56 | cap_offset + 12); |
| 57 | ret = (h << 32) | (l & ~0xfull); |
| 58 | break; |
| 59 | } |
| 60 | cap_offset += (es + 1) * 4; |
| 61 | ne--; |
| 62 | } |
| 63 | } else { |
| 64 | h = 0; |
| 65 | l = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0); |
| 66 | if (l & 4) |
| 67 | h = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0 |
| 68 | + 4); |
| 69 | ret = (h << 32) | (l & ~0xfull); |
| 70 | } |
| 71 | return ret; |
| 72 | } |