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Duncan Lauriec88c54c2014-04-30 16:36:13 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 * Copyright (C) 2014 Google Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Duncan Lauriec88c54c2014-04-30 16:36:13 -070015 */
16
17#ifndef _SOC_INTEL_BROADWELL_CHIP_H_
18#define _SOC_INTEL_BROADWELL_CHIP_H_
19
Elyes HAOUASc4e41932018-11-01 11:29:50 +010020#include <stdint.h>
21
Duncan Lauriec88c54c2014-04-30 16:36:13 -070022struct soc_intel_broadwell_config {
23 /*
24 * Interrupt Routing configuration
25 * If bit7 is 1, the interrupt is disabled.
26 */
27 uint8_t pirqa_routing;
28 uint8_t pirqb_routing;
29 uint8_t pirqc_routing;
30 uint8_t pirqd_routing;
31 uint8_t pirqe_routing;
32 uint8_t pirqf_routing;
33 uint8_t pirqg_routing;
34 uint8_t pirqh_routing;
35
36 /* GPE configuration */
37 uint32_t gpe0_en_1;
38 uint32_t gpe0_en_2;
39 uint32_t gpe0_en_3;
40 uint32_t gpe0_en_4;
41
42 /* GPIO SMI configuration */
43 uint32_t alt_gp_smi_en;
44
45 /* IDE configuration */
46 uint8_t sata_port_map;
47 uint32_t sata_port0_gen3_tx;
48 uint32_t sata_port1_gen3_tx;
Youness Alaoui696ebc22017-02-07 13:54:45 -050049 uint32_t sata_port2_gen3_tx;
50 uint32_t sata_port3_gen3_tx;
Duncan Lauriec88c54c2014-04-30 16:36:13 -070051 uint32_t sata_port0_gen3_dtle;
52 uint32_t sata_port1_gen3_dtle;
Youness Alaoui696ebc22017-02-07 13:54:45 -050053 uint32_t sata_port2_gen3_dtle;
54 uint32_t sata_port3_gen3_dtle;
Duncan Lauriec88c54c2014-04-30 16:36:13 -070055
56 /*
57 * SATA DEVSLP Mux
58 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
59 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
60 */
61 uint8_t sata_devslp_mux;
62
63 /*
64 * DEVSLP Disable
65 * 0: DEVSLP is enabled
66 * 1: DEVSLP is disabled
67 */
68 uint8_t sata_devslp_disable;
69
70 /* Generic IO decode ranges */
71 uint32_t gen1_dec;
72 uint32_t gen2_dec;
73 uint32_t gen3_dec;
74 uint32_t gen4_dec;
75
76 /* Enable linear PCIe Root Port function numbers starting at zero */
77 uint8_t pcie_port_coalesce;
78
79 /* Force root port ASPM configuration with port bitmap */
80 uint8_t pcie_port_force_aspm;
81
82 /* Put SerialIO devices into ACPI mode instead of a PCI device */
83 uint8_t sio_acpi_mode;
84
85 /* I2C voltage select: 0=3.3V 1=1.8V */
86 uint8_t sio_i2c0_voltage;
87 uint8_t sio_i2c1_voltage;
88
Duncan Lauried9f95072014-10-01 13:47:20 -070089 /* Enable ADSP power gating features */
90 uint8_t adsp_d3_pg_enable;
91 uint8_t adsp_sram_pg_enable;
Duncan Laurie3ed4d392014-07-31 10:41:56 -070092
Duncan Lauriec88c54c2014-04-30 16:36:13 -070093 /*
94 * Clock Disable Map:
95 * [21:16] = CLKOUT_PCIE# 5-0
96 * [24] = CLKOUT_ITPXDP
97 */
98 uint32_t icc_clock_disable;
99
100 /*
101 * Digital Port Hotplug Enable:
102 * 0x04 = Enabled, 2ms short pulse
103 * 0x05 = Enabled, 4.5ms short pulse
104 * 0x06 = Enabled, 6ms short pulse
105 * 0x07 = Enabled, 100ms short pulse
106 */
107 u8 gpu_dp_b_hotplug;
108 u8 gpu_dp_c_hotplug;
109 u8 gpu_dp_d_hotplug;
110
111 /* Panel power sequence timings */
112 u8 gpu_panel_port_select;
113 u8 gpu_panel_power_cycle_delay;
114 u16 gpu_panel_power_up_delay;
115 u16 gpu_panel_power_down_delay;
116 u16 gpu_panel_power_backlight_on_delay;
117 u16 gpu_panel_power_backlight_off_delay;
118
119 /* Panel backlight settings */
120 u32 gpu_cpu_backlight;
121 u32 gpu_pch_backlight;
122
123 /*
124 * Graphics CD Clock Frequency
125 * 0 = 337.5MHz
126 * 1 = 450MHz
127 * 2 = 540MHz
128 * 3 = 675MHz
129 */
130 int cdclk;
131
132 /* Enable S0iX support */
133 int s0ix_enable;
134
Duncan Laurieff0f4602015-01-20 07:53:27 -0800135 /*
136 * Minimum voltage for C6/C7 state:
137 * 0x67 = 1.6V (full swing)
138 * ...
139 * 0x79 = 1.7V
140 * ...
141 * 0x83 = 1.8V (no swing)
142 */
143 int vr_cpu_min_vid;
144
145 /*
146 * Set slow VR ramp rate on C-state exit:
147 * 0 = Fast VR ramp rate / 2
148 * 1 = Fast VR ramp rate / 4
149 * 2 = Fast VR ramp rate / 8
150 * 3 = Fast VR ramp rate / 16
151 */
152 int vr_slow_ramp_rate_set;
153
154 /* Enable slow VR ramp rate */
155 int vr_slow_ramp_rate_enable;
156
Duncan Laurie446fb8e2014-08-08 09:59:43 -0700157 /* Deep SX enable */
158 int deep_sx_enable_ac;
159 int deep_sx_enable_dc;
160
Duncan Lauriec88c54c2014-04-30 16:36:13 -0700161 /* TCC activation offset */
162 int tcc_offset;
163};
164
165typedef struct soc_intel_broadwell_config config_t;
166
Duncan Lauriec88c54c2014-04-30 16:36:13 -0700167#endif