blob: 118e646ee08dc865deeb68e63a5816b51affdfdd [file] [log] [blame]
Marc Jonesd8621212015-06-09 21:18:38 -06001chip soc/intel/broadwell
Marc Jones07cf24c2015-06-09 14:42:55 -06002
3 # Enable eDP Hotplug with 6ms pulse
4 register "gpu_dp_d_hotplug" = "0x06"
5
6 # Disable DisplayPort C Hotplug
7 register "gpu_dp_c_hotplug" = "0x00"
8
9 # Enable HDMI Hotplug with 6ms pulse
10 register "gpu_dp_b_hotplug" = "0x06"
11
12 # Set backlight PWM values for eDP
13 register "gpu_cpu_backlight" = "0x00000200"
14 register "gpu_pch_backlight" = "0x04000000"
15
16 # Enable Panel and configure power delays
17 register "gpu_panel_port_select" = "1" # eDP
18 register "gpu_panel_power_cycle_delay" = "5" # 400ms
19 register "gpu_panel_power_up_delay" = "400" # 40ms
20 register "gpu_panel_power_down_delay" = "150" # 15ms
Matt DeVillier45e11aa2016-12-18 11:59:58 -060021 register "gpu_panel_power_backlight_on_delay" = "500" # 50ms
Marc Jones07cf24c2015-06-09 14:42:55 -060022 register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
23
Marc Jonesd8621212015-06-09 21:18:38 -060024 register "pirqa_routing" = "0x8b"
25 register "pirqb_routing" = "0x8a"
26 register "pirqc_routing" = "0x8b"
27 register "pirqd_routing" = "0x8b"
28 register "pirqe_routing" = "0x80"
29 register "pirqf_routing" = "0x80"
30 register "pirqg_routing" = "0x80"
31 register "pirqh_routing" = "0x80"
32
33 # EC range is 0x800-0x9ff
34 register "gen1_dec" = "0x00fc0801"
35 register "gen2_dec" = "0x00fc0901"
36
37 # EC_SMI is GPIO34
38 register "alt_gp_smi_en" = "0x0004"
39 register "gpe0_en_1" = "0x00000000"
40 # EC_SCI is GPIO36
41 register "gpe0_en_2" = "0x00000010"
42 register "gpe0_en_3" = "0x00000000"
43 register "gpe0_en_4" = "0x00000000"
44
45 register "sata_port_map" = "0x1"
46 register "sio_acpi_mode" = "1"
47
48 # DTLE DATA / EDGE values
49 register "sata_port0_gen3_dtle" = "0x5"
50 register "sata_port1_gen3_dtle" = "0x5"
51
52 # Force enable ASPM for PCIe Port1
53 register "pcie_port_force_aspm" = "0x01"
54
55 # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
56 register "icc_clock_disable" = "0x013c0000"
57
58 register "s0ix_enable" = "1"
59
Marc Jones07cf24c2015-06-09 14:42:55 -060060 device cpu_cluster 0 on
Marc Jonesd8621212015-06-09 21:18:38 -060061 device lapic 0 on end
Marc Jones07cf24c2015-06-09 14:42:55 -060062 end
63
64 device domain 0 on
65 device pci 00.0 on end # host bridge
66 device pci 02.0 on end # vga controller
67 device pci 03.0 on end # mini-hd audio
Marc Jonesd8621212015-06-09 21:18:38 -060068 device pci 13.0 off end # Smart Sound Audio DSP
69 device pci 14.0 on end # USB3 XHCI
70 device pci 15.0 on end # Serial I/O DMA
71 device pci 15.1 on end # I2C0
72 device pci 15.2 on end # I2C1
73 device pci 15.3 off end # GSPI0
74 device pci 15.4 off end # GSPI1
75 device pci 15.5 off end # UART0
76 device pci 15.6 off end # UART1
77 device pci 16.0 on end # Management Engine Interface 1
78 device pci 16.1 off end # Management Engine Interface 2
79 device pci 16.2 off end # Management Engine IDE-R
80 device pci 16.3 off end # Management Engine KT
81 device pci 17.0 off end # SDIO
82 device pci 19.0 off end # GbE
83 device pci 1b.0 on end # High Definition Audio
84 device pci 1c.0 on end # PCIe Port #1
85 device pci 1c.1 off end # PCIe Port #2
86 device pci 1c.2 off end # PCIe Port #3
87 device pci 1c.3 off end # PCIe Port #4
88 device pci 1c.4 off end # PCIe Port #5
89 device pci 1c.5 off end # PCIe Port #6
90 device pci 1d.0 on end # USB2 EHCI
91 device pci 1e.0 off end # PCI bridge
92 device pci 1f.0 on
Matt DeVillier59962f32018-08-01 13:53:04 -050093 chip drivers/pc80/tpm
94 device pnp 0c31.0 on end
Marc Jonesd8621212015-06-09 21:18:38 -060095 end
96 chip ec/google/chromeec
97 device pnp 0c09.0 on end
98 end
99 end # LPC bridge
100 device pci 1f.2 on end # SATA Controller
101 device pci 1f.3 off end # SMBus
102 device pci 1f.6 on end # Thermal
Marc Jones07cf24c2015-06-09 14:42:55 -0600103 end
104end