blob: f75da84eee8ca65b36f8655b3f0d82e3bcb03d73 [file] [log] [blame]
Matt DeVillier1b25f1b2018-09-14 21:39:00 -05001chip soc/intel/broadwell
2
3 # Enable eDP Hotplug with 6ms pulse
4 register "gpu_dp_d_hotplug" = "0x06"
5
6 # Disable DisplayPort C Hotplug
7 register "gpu_dp_c_hotplug" = "0x00"
8
9 # Enable HDMI Hotplug with 6ms pulse
10 register "gpu_dp_b_hotplug" = "0x06"
11
12 # Set backlight PWM values for eDP
13 register "gpu_cpu_backlight" = "0x00000200"
14 register "gpu_pch_backlight" = "0x04000000"
15
16 # Enable Panel and configure power delays
17 register "gpu_panel_port_select" = "1" # eDP
18 register "gpu_panel_power_cycle_delay" = "5" # 400ms
19 register "gpu_panel_power_up_delay" = "400" # 40ms
20 register "gpu_panel_power_down_delay" = "150" # 15ms
21 register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
22 register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
23
24 register "pirqa_routing" = "0x8b"
25 register "pirqb_routing" = "0x8a"
26 register "pirqc_routing" = "0x8b"
27 register "pirqd_routing" = "0x8b"
28 register "pirqe_routing" = "0x80"
29 register "pirqf_routing" = "0x80"
30 register "pirqg_routing" = "0x80"
31 register "pirqh_routing" = "0x80"
32
33 # EC range is 0x800-0x9ff
34 register "gen1_dec" = "0x00fc0801"
35 register "gen2_dec" = "0x00fc0901"
36
37 # EC_SMI is GPIO34
38 register "alt_gp_smi_en" = "0x0004"
39 register "gpe0_en_1" = "0x00000000"
40 # EC_SCI is GPIO36
41 register "gpe0_en_2" = "0x00000010"
42 register "gpe0_en_3" = "0x00000000"
43 register "gpe0_en_4" = "0x00000000"
44
45 register "sata_port_map" = "0x1"
46 register "sata_devslp_disable" = "0x1"
47
48 register "sio_acpi_mode" = "1"
49 register "sio_i2c0_voltage" = "1" # 1.8V
50 register "sio_i2c1_voltage" = "0" # 3.3V
51
52 # DTLE DATA / EDGE values
53 register "sata_port0_gen3_dtle" = "0x5"
54 register "sata_port1_gen3_dtle" = "0x5"
55
56 # Force enable ASPM for PCIe Port 5
57 register "pcie_port_force_aspm" = "0x10"
58
59 # Enable port coalescing
60 register "pcie_port_coalesce" = "1"
61
62 # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
63 register "icc_clock_disable" = "0x01220000"
64
65 register "s0ix_enable" = "0"
66
67 device cpu_cluster 0 on
68 device lapic 0 on end
69 end
70
71 device domain 0 on
72 device pci 00.0 on end # host bridge
73 device pci 02.0 on end # vga controller
74 device pci 03.0 on end # mini-hd audio
75 device pci 13.0 on end # Smart Sound Audio DSP
76 device pci 14.0 on end # USB3 XHCI
77 device pci 15.0 on end # Serial I/O DMA
78 device pci 15.1 on end # I2C0
79 device pci 15.2 on end # I2C1
80 device pci 15.3 off end # GSPI0
81 device pci 15.4 off end # GSPI1
82 device pci 15.5 off end # UART0
83 device pci 15.6 off end # UART1
84 device pci 16.0 on end # Management Engine Interface 1
85 device pci 16.1 off end # Management Engine Interface 2
86 device pci 16.2 off end # Management Engine IDE-R
87 device pci 16.3 off end # Management Engine KT
88 device pci 17.0 off end # SDIO
89 device pci 19.0 off end # GbE
90 device pci 1b.0 off end # High Definition Audio
91 device pci 1c.0 off end # PCIe Port #1
92 device pci 1c.1 off end # PCIe Port #2
Matt DeVilliera82f9912018-12-29 21:43:11 -060093 device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1)
94 device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2)
Matt DeVillier1b25f1b2018-09-14 21:39:00 -050095 device pci 1c.4 on end # PCIe Port #5
96 device pci 1c.5 off end # PCIe Port #6
97 device pci 1d.0 on end # USB2 EHCI
98 device pci 1e.0 off end # PCI bridge
99 device pci 1f.0 on
100 chip drivers/pc80/tpm
101 device pnp 0c31.0 on end
102 end
103 chip ec/google/chromeec
104 device pnp 0c09.0 on end
105 end
106 end # LPC bridge
107 device pci 1f.2 on end # SATA Controller
108 device pci 1f.3 on end # SMBus
109 device pci 1f.6 on end # Thermal
110 end
111end