Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ICELAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Icelake support |
| 5 | |
| 6 | if SOC_INTEL_ICELAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| 11 | select ARCH_BOOTBLOCK_X86_32 |
| 12 | select ARCH_RAMSTAGE_X86_32 |
| 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
| 15 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 16 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 17 | select C_ENVIRONMENT_BOOTBLOCK |
| 18 | select CACHE_MRC_SETTINGS |
| 19 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
| 20 | select COMMON_FADT |
| 21 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Subrata Banik | ffb83be | 2019-04-29 13:58:43 +0530 | [diff] [blame] | 22 | select FSP_M_XIP |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 23 | select GENERIC_GPIO_LIB |
| 24 | select HAVE_FSP_GOP |
| 25 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 26 | select HAVE_MONOTONIC_TIMER |
| 27 | select HAVE_SMI_HANDLER |
| 28 | select IDT_IN_EVERY_STAGE |
| 29 | select INTEL_GMA_ACPI |
| 30 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 31 | select IOAPIC |
| 32 | select MRC_SETTINGS_PROTECT |
| 33 | select PARALLEL_MP |
| 34 | select PARALLEL_MP_AP_WORK |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 35 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | 55fb6b4 | 2018-12-19 16:50:57 +0530 | [diff] [blame] | 36 | select PLATFORM_USES_FSP2_1 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 37 | select POSTCAR_CONSOLE |
| 38 | select POSTCAR_STAGE |
| 39 | select REG_SCRIPT |
| 40 | select SMM_TSEG |
| 41 | select SMP |
| 42 | select SOC_AHCI_PORT_IMPLEMENTED_INVERT |
| 43 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
| 44 | select SOC_INTEL_COMMON |
| 45 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 46 | select SOC_INTEL_COMMON_BLOCK |
| 47 | select SOC_INTEL_COMMON_BLOCK_ACPI |
| 48 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
| 49 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 50 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 51 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 52 | select SOC_INTEL_COMMON_BLOCK_HDA |
| 53 | select SOC_INTEL_COMMON_BLOCK_SA |
| 54 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 55 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
| 56 | select SOC_INTEL_COMMON_PCH_BASE |
| 57 | select SOC_INTEL_COMMON_RESET |
| 58 | select SSE2 |
| 59 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 60 | select TSC_CONSTANT_RATE |
| 61 | select TSC_MONOTONIC_TIMER |
| 62 | select UDELAY_TSC |
| 63 | select UDK_2017_BINDING |
| 64 | select DISPLAY_FSP_VERSION_INFO |
| 65 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 66 | config DCACHE_RAM_BASE |
| 67 | default 0xfef00000 |
| 68 | |
| 69 | config DCACHE_RAM_SIZE |
| 70 | default 0x40000 |
| 71 | help |
| 72 | The size of the cache-as-ram region required during bootblock |
| 73 | and/or romstage. |
| 74 | |
| 75 | config DCACHE_BSP_STACK_SIZE |
| 76 | hex |
Aamir Bohra | 23012a0 | 2018-10-09 20:33:16 +0530 | [diff] [blame] | 77 | default 0x20000 if FSP_USES_CB_STACK |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 78 | default 0x4000 |
| 79 | help |
| 80 | The amount of anticipated stack usage in CAR by bootblock and |
| 81 | other stages. |
| 82 | |
| 83 | config IFD_CHIPSET |
| 84 | string |
| 85 | default "icl" |
| 86 | |
| 87 | config IED_REGION_SIZE |
| 88 | hex |
| 89 | default 0x400000 |
| 90 | |
| 91 | config HEAP_SIZE |
| 92 | hex |
| 93 | default 0x8000 |
| 94 | |
| 95 | config MAX_ROOT_PORTS |
| 96 | int |
| 97 | default 16 |
| 98 | |
| 99 | config SMM_TSEG_SIZE |
| 100 | hex |
| 101 | default 0x800000 |
| 102 | |
| 103 | config SMM_RESERVED_SIZE |
| 104 | hex |
| 105 | default 0x200000 |
| 106 | |
| 107 | config PCR_BASE_ADDRESS |
| 108 | hex |
| 109 | default 0xfd000000 |
| 110 | help |
| 111 | This option allows you to select MMIO Base Address of sideband bus. |
| 112 | |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 113 | config MMCONF_BASE_ADDRESS |
| 114 | hex |
| 115 | default 0xc0000000 |
| 116 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 117 | config CPU_BCLK_MHZ |
| 118 | int |
| 119 | default 100 |
| 120 | |
| 121 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 122 | int |
| 123 | default 120 |
| 124 | |
| 125 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 126 | int |
| 127 | default 133 |
| 128 | |
| 129 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 130 | int |
| 131 | default 3 |
| 132 | |
| 133 | config SOC_INTEL_I2C_DEV_MAX |
| 134 | int |
| 135 | default 6 |
| 136 | |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 137 | config SOC_INTEL_UART_DEV_MAX |
| 138 | int |
| 139 | default 3 |
| 140 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 141 | # Clock divider parameters for 115200 baud rate |
| 142 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 143 | hex |
| 144 | default 0x30 |
| 145 | |
| 146 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 147 | hex |
| 148 | default 0xc35 |
| 149 | |
| 150 | config CHROMEOS |
| 151 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 152 | |
| 153 | config VBOOT |
| 154 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 155 | select VBOOT_MUST_REQUEST_DISPLAY |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 156 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
| 157 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 158 | select VBOOT_VBNV_CMOS |
| 159 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 160 | |
| 161 | config C_ENV_BOOTBLOCK_SIZE |
| 162 | hex |
Subrata Banik | 458297c | 2019-01-07 14:24:27 +0530 | [diff] [blame] | 163 | default 0xC000 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 164 | |
| 165 | config CBFS_SIZE |
| 166 | hex |
| 167 | default 0x200000 |
| 168 | |
| 169 | choice |
| 170 | prompt "Cache-as-ram implementation" |
| 171 | default USE_ICELAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS |
| 172 | default USE_ICELAKE_FSP_CAR |
| 173 | help |
| 174 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 175 | |
| 176 | config USE_ICELAKE_CAR_NEM_ENHANCED |
| 177 | bool "Enhanced Non-evict mode" |
| 178 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 179 | select INTEL_CAR_NEM_ENHANCED |
| 180 | help |
| 181 | A current limitation of NEM (Non-Evict mode) is that code and data |
| 182 | sizes are derived from the requirement to not write out any modified |
| 183 | cache line. With NEM, if there is no physical memory behind the |
| 184 | cached area, the modified data will be lost and NEM results will be |
| 185 | inconsistent. ENHANCED NEM guarantees that modified data is always |
| 186 | kept in cache while clean data is replaced. |
| 187 | |
| 188 | config USE_ICELAKE_FSP_CAR |
| 189 | bool "Use FSP CAR" |
| 190 | select FSP_CAR |
| 191 | help |
| 192 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
| 193 | |
| 194 | endchoice |
| 195 | |
| 196 | config FSP_HEADER_PATH |
Patrick Georgi | c6382cd | 2018-10-26 22:03:17 +0200 | [diff] [blame] | 197 | string "Location of FSP headers" |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 198 | default "src/vendorcode/intel/fsp/fsp2_0/icelake/" |
| 199 | |
| 200 | config FSP_FD_PATH |
| 201 | string |
| 202 | depends on FSP_USE_REPO |
| 203 | default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" |
| 204 | |
| 205 | endif |