Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <stdlib.h> |
| 27 | #include <string.h> |
| 28 | #include <reg_script.h> |
| 29 | #include <drivers/intel/gma/i915_reg.h> |
| 30 | #include <broadwell/cpu.h> |
| 31 | #include <broadwell/ramstage.h> |
| 32 | #include <broadwell/systemagent.h> |
| 33 | #include <chip.h> |
| 34 | |
| 35 | #define GT_RETRY 1000 |
| 36 | #define GT_CDCLK_337 0 |
| 37 | #define GT_CDCLK_450 1 |
| 38 | #define GT_CDCLK_540 2 |
| 39 | #define GT_CDCLK_675 3 |
| 40 | |
| 41 | struct reg_script haswell_early_init_script[] = { |
| 42 | /* Enable Force Wake */ |
| 43 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), |
| 44 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), |
| 45 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 1, GT_RETRY), |
| 46 | |
| 47 | /* Enable Counters */ |
| 48 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), |
| 49 | |
| 50 | /* GFXPAUSE settings */ |
| 51 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020), |
| 52 | |
| 53 | /* ECO Settings */ |
| 54 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000), |
| 55 | |
| 56 | /* Enable DOP Clock Gating */ |
| 57 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd), |
| 58 | |
| 59 | /* Enable Unit Level Clock Gating */ |
| 60 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080), |
| 61 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000), |
| 62 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000), |
| 63 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001), |
| 64 | |
| 65 | /* |
| 66 | * RC6 Settings |
| 67 | */ |
| 68 | |
| 69 | /* Wake Rate Limits */ |
| 70 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa090, 0x00000000), |
| 71 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa098, 0x03e80000), |
| 72 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa09c, 0x00280000), |
| 73 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0a8, 0x0001e848), |
| 74 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0ac, 0x00000019), |
| 75 | |
| 76 | /* Render/Video/Blitter Idle Max Count */ |
| 77 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a), |
| 78 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a), |
| 79 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a), |
| 80 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a), |
| 81 | |
| 82 | /* RC Sleep / RCx Thresholds */ |
| 83 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b0, 0x00000000), |
| 84 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b4, 0x000003e8), |
| 85 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b8, 0x0000c350), |
| 86 | |
| 87 | /* RP Settings */ |
| 88 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa010, 0x000f4240), |
| 89 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa014, 0x12060000), |
| 90 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa02c, 0x0000e808), |
| 91 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa030, 0x0003bd08), |
| 92 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa068, 0x000101d0), |
| 93 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa06c, 0x00055730), |
| 94 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a), |
| 95 | |
| 96 | /* RP Control */ |
| 97 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92), |
| 98 | |
| 99 | /* HW RC6 Control */ |
| 100 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x88040000), |
| 101 | |
| 102 | /* Video Frequency Request */ |
| 103 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000), |
| 104 | |
| 105 | /* Set RC6 VIDs */ |
| 106 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 107 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), |
| 108 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), |
| 109 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 110 | |
| 111 | /* Enable PM Interrupts */ |
| 112 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), |
| 113 | |
| 114 | /* Enable RC6 in idle */ |
| 115 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000), |
| 116 | |
| 117 | REG_SCRIPT_END |
| 118 | }; |
| 119 | |
| 120 | static const struct reg_script haswell_late_init_script[] = { |
| 121 | /* Lock settings */ |
| 122 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)), |
| 123 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a004, (1 << 4)), |
| 124 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a080, (1 << 2)), |
| 125 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)), |
| 126 | |
| 127 | /* Disable Force Wake */ |
| 128 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), |
| 129 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 0, GT_RETRY), |
| 130 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001), |
| 131 | |
| 132 | /* Enable power well for DP and Audio */ |
| 133 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), |
| 134 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, |
| 135 | (1 << 30), (1 << 30), GT_RETRY), |
| 136 | |
| 137 | REG_SCRIPT_END |
| 138 | }; |
| 139 | |
| 140 | static const struct reg_script broadwell_early_init_script[] = { |
| 141 | /* Enable Force Wake */ |
| 142 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), |
| 143 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 1, GT_RETRY), |
| 144 | |
| 145 | /* Enable push bus metric control and shift */ |
| 146 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004), |
| 147 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff), |
| 148 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010), |
| 149 | |
| 150 | /* GFXPAUSE settings */ |
| 151 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00030020), |
| 152 | |
| 153 | /* ECO Settings */ |
| 154 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000), |
| 155 | |
| 156 | /* Enable DOP Clock Gating */ |
| 157 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000000fd), |
| 158 | |
| 159 | /* Enable Unit Level Clock Gating */ |
| 160 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000000), |
| 161 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000), |
| 162 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000), |
| 163 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001), |
| 164 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a), |
| 165 | |
| 166 | /* Video Frequency Request */ |
| 167 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000), |
| 168 | |
| 169 | /* |
| 170 | * RC6 Settings |
| 171 | */ |
| 172 | |
| 173 | /* Wake Rate Limits */ |
| 174 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0a090, 0, 0), |
| 175 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a098, 0x03e80000), |
| 176 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a09c, 0x00280000), |
| 177 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0a8, 0x0001e848), |
| 178 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0ac, 0x00000019), |
| 179 | |
| 180 | /* Render/Video/Blitter Idle Max Count */ |
| 181 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a), |
| 182 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a), |
| 183 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a), |
| 184 | |
| 185 | /* RC Sleep / RCx Thresholds */ |
| 186 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b0, 0x00000000), |
| 187 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b8, 0x00000271), |
| 188 | |
| 189 | /* RP Settings */ |
| 190 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a010, 0x000f4240), |
| 191 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a014, 0x12060000), |
| 192 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a02c, 0x0000e808), |
| 193 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a030, 0x0003bd08), |
| 194 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a068, 0x000101d0), |
| 195 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a06c, 0x00055730), |
| 196 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a070, 0x0000000a), |
| 197 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a168, 0x00000006), |
| 198 | |
| 199 | /* RP Control */ |
| 200 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92), |
| 201 | |
| 202 | /* HW RC6 Control */ |
| 203 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000), |
| 204 | |
| 205 | /* Set RC6 VIDs */ |
| 206 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 207 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), |
| 208 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), |
| 209 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 210 | |
| 211 | /* Enable PM Interrupts */ |
| 212 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), |
| 213 | |
| 214 | /* Enable RC6 in idle */ |
| 215 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000), |
| 216 | |
| 217 | REG_SCRIPT_END |
| 218 | }; |
| 219 | |
| 220 | static const struct reg_script broadwell_late_init_script[] = { |
| 221 | /* Lock settings */ |
| 222 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)), |
| 223 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a000, (1 << 18)), |
| 224 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)), |
| 225 | |
| 226 | /* Disable Force Wake */ |
| 227 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), |
| 228 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 0, GT_RETRY), |
| 229 | |
| 230 | /* Enable power well for DP and Audio */ |
| 231 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), |
| 232 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, |
| 233 | (1 << 30), (1 << 30), GT_RETRY), |
| 234 | |
| 235 | REG_SCRIPT_END |
| 236 | }; |
| 237 | |
| 238 | u32 map_oprom_vendev(u32 vendev) |
| 239 | { |
| 240 | return SA_IGD_OPROM_VENDEV; |
| 241 | } |
| 242 | |
| 243 | static struct resource *gtt_res = NULL; |
| 244 | |
| 245 | static unsigned long gtt_read(unsigned long reg) |
| 246 | { |
| 247 | u32 val; |
| 248 | val = read32(gtt_res->base + reg); |
| 249 | return val; |
| 250 | |
| 251 | } |
| 252 | |
| 253 | static void gtt_write(unsigned long reg, unsigned long data) |
| 254 | { |
| 255 | write32(gtt_res->base + reg, data); |
| 256 | } |
| 257 | |
| 258 | static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) |
| 259 | { |
| 260 | u32 val = gtt_read(reg); |
| 261 | val &= andmask; |
| 262 | val |= ormask; |
| 263 | gtt_write(reg, val); |
| 264 | } |
| 265 | |
| 266 | static int gtt_poll(u32 reg, u32 mask, u32 value) |
| 267 | { |
| 268 | unsigned try = GT_RETRY; |
| 269 | u32 data; |
| 270 | |
| 271 | while (try--) { |
| 272 | data = gtt_read(reg); |
| 273 | if ((data & mask) == value) |
| 274 | return 1; |
| 275 | udelay(10); |
| 276 | } |
| 277 | |
| 278 | printk(BIOS_ERR, "GT init timeout\n"); |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | static void igd_setup_panel(struct device *dev) |
| 283 | { |
| 284 | config_t *conf = dev->chip_info; |
| 285 | u32 reg32; |
| 286 | |
| 287 | /* Setup Digital Port Hotplug */ |
| 288 | reg32 = gtt_read(PCH_PORT_HOTPLUG); |
| 289 | if (!reg32) { |
| 290 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 291 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 292 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 293 | gtt_write(PCH_PORT_HOTPLUG, reg32); |
| 294 | } |
| 295 | |
| 296 | /* Setup Panel Power On Delays */ |
| 297 | reg32 = gtt_read(PCH_PP_ON_DELAYS); |
| 298 | if (!reg32) { |
| 299 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 300 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 301 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 302 | gtt_write(PCH_PP_ON_DELAYS, reg32); |
| 303 | } |
| 304 | |
| 305 | /* Setup Panel Power Off Delays */ |
| 306 | reg32 = gtt_read(PCH_PP_OFF_DELAYS); |
| 307 | if (!reg32) { |
| 308 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 309 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 310 | gtt_write(PCH_PP_OFF_DELAYS, reg32); |
| 311 | } |
| 312 | |
| 313 | /* Setup Panel Power Cycle Delay */ |
| 314 | if (conf->gpu_panel_power_cycle_delay) { |
| 315 | reg32 = gtt_read(PCH_PP_DIVISOR); |
| 316 | reg32 &= ~0xff; |
| 317 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 318 | gtt_write(PCH_PP_DIVISOR, reg32); |
| 319 | } |
| 320 | |
| 321 | /* Enable Backlight if needed */ |
| 322 | if (conf->gpu_cpu_backlight) { |
| 323 | gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); |
| 324 | gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); |
| 325 | } |
| 326 | if (conf->gpu_pch_backlight) { |
| 327 | gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); |
| 328 | gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | static void igd_cdclk_init_haswell(struct device *dev) |
| 333 | { |
| 334 | config_t *conf = dev->chip_info; |
| 335 | int cdclk = conf->cdclk; |
| 336 | int devid = pci_read_config16(dev, PCI_DEVICE_ID); |
| 337 | int gpu_is_ulx = 0; |
| 338 | u32 dpdiv, lpcll; |
| 339 | |
| 340 | /* Check for ULX GT1 or GT2 */ |
| 341 | if (devid == 0x0a0e || devid == 0x0a1e) |
| 342 | gpu_is_ulx = 1; |
| 343 | |
| 344 | /* 675MHz is not supported on haswell */ |
| 345 | if (cdclk == GT_CDCLK_675) |
| 346 | cdclk = GT_CDCLK_337; |
| 347 | |
| 348 | /* If CD clock is fixed or ULT then set to 450MHz */ |
| 349 | if ((gtt_read(0x42014) & 0x1000000) || cpu_is_ult()) |
| 350 | cdclk = GT_CDCLK_450; |
| 351 | |
| 352 | /* 540MHz is not supported on ULX */ |
| 353 | if (gpu_is_ulx && cdclk == GT_CDCLK_540) |
| 354 | cdclk = GT_CDCLK_337; |
| 355 | |
| 356 | /* 337.5MHz is not supported on non-ULT/ULX */ |
| 357 | if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337) |
| 358 | cdclk = GT_CDCLK_450; |
| 359 | |
| 360 | /* Set variables based on CD Clock setting */ |
| 361 | switch (cdclk) { |
| 362 | case GT_CDCLK_337: |
| 363 | dpdiv = 169; |
| 364 | lpcll = (1 << 26); |
| 365 | break; |
| 366 | case GT_CDCLK_450: |
| 367 | dpdiv = 225; |
| 368 | lpcll = 0; |
| 369 | break; |
| 370 | case GT_CDCLK_540: |
| 371 | dpdiv = 270; |
| 372 | lpcll = (1 << 26); |
| 373 | break; |
| 374 | default: |
| 375 | return; |
| 376 | } |
| 377 | |
| 378 | /* Set LPCLL_CTL CD Clock Frequency Select */ |
| 379 | gtt_rmw(0x130040, 0xf3ffffff, lpcll); |
| 380 | |
| 381 | /* ULX: Inform power controller of selected frequency */ |
| 382 | if (gpu_is_ulx) { |
| 383 | if (cdclk == GT_CDCLK_450) |
| 384 | gtt_write(0x138128, 0x00000000); /* 450MHz */ |
| 385 | else |
| 386 | gtt_write(0x138128, 0x00000001); /* 337.5MHz */ |
| 387 | gtt_write(0x13812c, 0x00000000); |
| 388 | gtt_write(0x138124, 0x80000017); |
| 389 | } |
| 390 | |
| 391 | /* Set CPU DP AUX 2X bit clock dividers */ |
| 392 | gtt_rmw(0x64010, 0xfffff800, dpdiv); |
| 393 | gtt_rmw(0x64810, 0xfffff800, dpdiv); |
| 394 | } |
| 395 | |
| 396 | static void igd_cdclk_init_broadwell(struct device *dev) |
| 397 | { |
| 398 | config_t *conf = dev->chip_info; |
| 399 | int cdclk = conf->cdclk; |
| 400 | u32 dpdiv, lpcll, pwctl, cdset; |
| 401 | |
| 402 | /* Inform power controller of upcoming frequency change */ |
| 403 | gtt_write(0x138128, 0); |
| 404 | gtt_write(0x13812c, 0); |
| 405 | gtt_write(0x138124, 0x80000018); |
| 406 | |
| 407 | /* Poll GT driver mailbox for run/busy clear */ |
| 408 | if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) |
| 409 | cdclk = GT_CDCLK_450; |
| 410 | |
| 411 | if (gtt_read(0x42014) & 0x1000000) { |
| 412 | /* If CD clock is fixed then set to 450MHz */ |
| 413 | cdclk = GT_CDCLK_450; |
| 414 | } else { |
| 415 | /* Program CD clock to highest supported freq */ |
| 416 | if (cpu_is_ult()) |
| 417 | cdclk = GT_CDCLK_540; |
| 418 | else |
| 419 | cdclk = GT_CDCLK_675; |
| 420 | } |
| 421 | |
| 422 | /* CD clock frequency 675MHz not supported on ULT */ |
| 423 | if (cpu_is_ult() && cdclk == GT_CDCLK_675) |
| 424 | cdclk = GT_CDCLK_540; |
| 425 | |
| 426 | /* Set variables based on CD Clock setting */ |
| 427 | switch (cdclk) { |
| 428 | case GT_CDCLK_337: |
| 429 | cdset = 337; |
| 430 | lpcll = (1 << 27); |
| 431 | pwctl = 2; |
| 432 | dpdiv = 169; |
| 433 | break; |
| 434 | case GT_CDCLK_450: |
| 435 | cdset = 449; |
| 436 | lpcll = 0; |
| 437 | pwctl = 0; |
| 438 | dpdiv = 225; |
| 439 | break; |
| 440 | case GT_CDCLK_540: |
| 441 | cdset = 539; |
| 442 | lpcll = (1 << 26); |
| 443 | pwctl = 1; |
| 444 | dpdiv = 270; |
| 445 | break; |
| 446 | case GT_CDCLK_675: |
| 447 | cdset = 674; |
| 448 | lpcll = (1 << 26) | (1 << 27); |
| 449 | pwctl = 3; |
| 450 | dpdiv = 338; |
| 451 | default: |
| 452 | return; |
| 453 | } |
| 454 | |
| 455 | /* Set LPCLL_CTL CD Clock Frequency Select */ |
| 456 | gtt_rmw(0x130040, 0xf3ffffff, lpcll); |
| 457 | |
| 458 | /* Inform power controller of selected frequency */ |
| 459 | gtt_write(0x138128, pwctl); |
| 460 | gtt_write(0x13812c, 0); |
| 461 | gtt_write(0x138124, 0x80000017); |
| 462 | |
| 463 | /* Program CD Clock Frequency */ |
| 464 | gtt_rmw(0x46200, 0xfffffc00, cdset); |
| 465 | |
| 466 | /* Set CPU DP AUX 2X bit clock dividers */ |
| 467 | gtt_rmw(0x64010, 0xfffff800, dpdiv); |
| 468 | gtt_rmw(0x64810, 0xfffff800, dpdiv); |
| 469 | } |
| 470 | |
| 471 | static void igd_init(struct device *dev) |
| 472 | { |
| 473 | int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); |
| 474 | u32 rp1_gfx_freq; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 475 | extern int oprom_is_loaded; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 476 | |
| 477 | /* IGD needs to be Bus Master */ |
| 478 | u32 reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 479 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 480 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 481 | |
| 482 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 483 | if (!gtt_res || !gtt_res->base) |
| 484 | return; |
| 485 | |
| 486 | /* Wait for any configured pre-graphics delay */ |
| 487 | mdelay(CONFIG_PRE_GRAPHICS_DELAY); |
| 488 | |
| 489 | /* Early init steps */ |
| 490 | if (is_broadwell) { |
| 491 | reg_script_run_on_dev(dev, broadwell_early_init_script); |
| 492 | } else { |
| 493 | reg_script_run_on_dev(dev, haswell_early_init_script); |
| 494 | } |
| 495 | |
| 496 | /* Set RP1 graphics frequency */ |
| 497 | rp1_gfx_freq = (MCHBAR32(0x5998) >> 8) & 0xff; |
| 498 | gtt_write(0xa008, rp1_gfx_freq << 24); |
| 499 | |
| 500 | /* Post VBIOS panel setup */ |
| 501 | igd_setup_panel(dev); |
| 502 | |
| 503 | /* Initialize PCI device, load/execute BIOS Option ROM */ |
| 504 | pci_dev_init(dev); |
| 505 | |
| 506 | /* Late init steps */ |
| 507 | if (is_broadwell) { |
| 508 | igd_cdclk_init_broadwell(dev); |
| 509 | reg_script_run_on_dev(dev, broadwell_late_init_script); |
| 510 | } else { |
| 511 | igd_cdclk_init_haswell(dev); |
| 512 | reg_script_run_on_dev(dev, haswell_late_init_script); |
| 513 | } |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 514 | |
| 515 | if (!oprom_is_loaded) { |
| 516 | /* |
| 517 | * Enable DDI-A if the Option ROM did not execute: |
| 518 | * |
| 519 | * bit 0: Display detected (RO) |
| 520 | * bit 4: DDI A supports 4 lanes and DDI E is not used |
| 521 | * bit 7: DDI buffer is idle |
| 522 | */ |
| 523 | gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | |
| 524 | DDI_INIT_DISPLAY_DETECTED); |
| 525 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 526 | } |
| 527 | |
| 528 | static void igd_read_resources(struct device *dev) |
| 529 | { |
| 530 | pci_dev_read_resources(dev); |
| 531 | |
| 532 | #if CONFIG_MARK_GRAPHICS_MEM_WRCOMB |
| 533 | struct resource *res; |
| 534 | |
| 535 | /* Set the graphics memory to write combining. */ |
| 536 | res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 537 | if (res == NULL) { |
| 538 | printk(BIOS_DEBUG, "gma: memory resource not found.\n"); |
| 539 | return; |
| 540 | } |
| 541 | res->flags |= IORESOURCE_WRCOMB; |
| 542 | #endif |
| 543 | } |
| 544 | |
| 545 | static struct device_operations igd_ops = { |
| 546 | .read_resources = &igd_read_resources, |
| 547 | .set_resources = &pci_dev_set_resources, |
| 548 | .enable_resources = &pci_dev_enable_resources, |
| 549 | .init = &igd_init, |
| 550 | .ops_pci = &broadwell_pci_ops, |
| 551 | }; |
| 552 | |
| 553 | static const unsigned short pci_device_ids[] = { |
| 554 | IGD_HASWELL_ULT_GT1, |
| 555 | IGD_HASWELL_ULT_GT2, |
| 556 | IGD_HASWELL_ULT_GT3, |
| 557 | IGD_BROADWELL_U_GT1, |
| 558 | IGD_BROADWELL_U_GT2, |
| 559 | IGD_BROADWELL_U_GT3_15W, |
| 560 | IGD_BROADWELL_U_GT3_28W, |
| 561 | IGD_BROADWELL_Y_GT2, |
| 562 | IGD_BROADWELL_H_GT2, |
| 563 | IGD_BROADWELL_H_GT3, |
| 564 | 0, |
| 565 | }; |
| 566 | |
| 567 | static const struct pci_driver igd_driver __pci_driver = { |
| 568 | .ops = &igd_ops, |
| 569 | .vendor = PCI_VENDOR_ID_INTEL, |
| 570 | .devices = pci_device_ids, |
| 571 | }; |