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Kyösti Mälkkie8b4da22014-10-21 18:22:32 +03001##
2## This file is part of the coreboot project.
3##
Marc Jonesa84fa902016-09-20 20:33:42 -06004## Copyright (C) 2010-2016 Advanced Micro Devices, Inc.
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +03005##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030015
Dave Frodinef9a4e62015-01-27 07:16:03 -070016config SOUTHBRIDGE_AMD_PI_BOLTON
17 bool
Dave Frodinef9a4e62015-01-27 07:16:03 -070018
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030019config SOUTHBRIDGE_AMD_PI_AVALON
20 bool
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030021
WANG Siyuanf2dfef02015-05-20 14:41:01 +080022config SOUTHBRIDGE_AMD_PI_KERN
23 bool
WANG Siyuanf2dfef02015-05-20 14:41:01 +080024
Martin Rothba566bd2015-06-28 09:44:31 -060025config HUDSON_DISABLE_IMC
26 bool
27
WANG Siyuanf2dfef02015-05-20 14:41:01 +080028if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030029
Nico Huberf4181052018-10-07 13:25:59 +020030config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
31 def_bool y
32 select IOAPIC
33 select HAVE_USBDEBUG_OPTIONS
34 select HAVE_CF9_RESET
35 select HAVE_CF9_RESET_PREPARE
36
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030037config BOOTBLOCK_SOUTHBRIDGE_INIT
38 string
Dave Frodinbc21a412015-01-19 11:40:38 -070039 default "southbridge/amd/pi/hudson/bootblock.c"
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030040
41config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT
42 bool
43 default n
44
45config EHCI_BAR
46 hex
47 default 0xfef00000
48
49config HUDSON_XHCI_ENABLE
50 bool "Enable Hudson XHCI Controller"
51 default y
52 help
53 The XHCI controller must be enabled and the XHCI firmware
54 must be added in order to have USB 3.0 support configured
55 by coreboot. The OS will be responsible for enabling the XHCI
56 controller if the the XHCI firmware is available but the
57 XHCI controller is not enabled by coreboot.
58
59config HUDSON_XHCI_FWM
60 bool "Add xhci firmware"
61 default y
62 help
63 Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
64
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030065config HUDSON_IMC_FWM
66 bool "Add IMC firmware"
67 depends on !HUDSON_DISABLE_IMC
68 default y
Dave Frodinfedd8e32015-01-21 07:26:26 -070069 help
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030070 Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
71
72config HUDSON_GEC_FWM
73 bool
74 default n
Dave Frodinfedd8e32015-01-21 07:26:26 -070075 help
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030076 Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
77 Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
78
79config HUDSON_PSP
80 bool
Kyösti Mälkkifa2786a2017-07-07 23:05:40 +030081 default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030082
83config HUDSON_XHCI_FWM_FILE
Dave Frodinfedd8e32015-01-21 07:26:26 -070084 string "XHCI firmware path and filename"
Patrick Georgi26e24cc2015-05-05 22:27:25 +020085 default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuanf2dfef02015-05-20 14:41:01 +080086 default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030087 depends on HUDSON_XHCI_FWM
88
89config HUDSON_IMC_FWM_FILE
Dave Frodinfedd8e32015-01-21 07:26:26 -070090 string "IMC firmware path and filename"
Patrick Georgi26e24cc2015-05-05 22:27:25 +020091 default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuanf2dfef02015-05-20 14:41:01 +080092 default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030093 depends on HUDSON_IMC_FWM
94
95config HUDSON_GEC_FWM_FILE
Dave Frodinfedd8e32015-01-21 07:26:26 -070096 string "GEC firmware path and filename"
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030097 depends on HUDSON_GEC_FWM
98
99config HUDSON_FWM
100 bool
101 default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM || HUDSON_GEC_FWM || HUDSON_PSP
102 default n
103
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300104config AMD_PUBKEY_FILE
Dave Frodinfedd8e32015-01-21 07:26:26 -0700105 depends on HUDSON_PSP
106 string "AMD public Key"
Patrick Georgi26e24cc2015-05-05 22:27:25 +0200107 default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
WANG Siyuanf2dfef02015-05-20 14:41:01 +0800108 default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyCZ.bin" if CPU_AMD_PI_00660F01
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300109
110config HUDSON_SATA_MODE
Dave Frodinfedd8e32015-01-21 07:26:26 -0700111 int "SATA Mode"
112 default 0
113 range 0 6
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300114 help
115 Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
116 The default is NATIVE.
117 0: NATIVE mode does not require a ROM.
118 1: RAID mode must have the two ROM files.
119 2: AHCI may work with or without AHCI ROM. It depends on the payload support.
120 For example, seabios does not require the AHCI ROM.
121 3: LEGACY IDE
122 4: IDE to AHCI
123 5: AHCI7804: ROM Required, and AMD driver required in the OS.
124 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
125
126comment "NATIVE"
127 depends on HUDSON_SATA_MODE = 0
128
129comment "RAID"
130 depends on HUDSON_SATA_MODE = 1
131
132comment "AHCI"
133 depends on HUDSON_SATA_MODE = 2
134
135comment "LEGACY IDE"
136 depends on HUDSON_SATA_MODE = 3
137
138comment "IDE to AHCI"
139 depends on HUDSON_SATA_MODE = 4
140
141comment "AHCI7804"
142 depends on HUDSON_SATA_MODE = 5
143
144comment "IDE to AHCI7804"
145 depends on HUDSON_SATA_MODE = 6
146
147if HUDSON_SATA_MODE = 2 || HUDSON_SATA_MODE = 5
148
149config AHCI_ROM_ID
150 string "AHCI device PCI IDs"
151 default "1022,7801" if HUDSON_SATA_MODE = 2
152 default "1022,7804" if HUDSON_SATA_MODE = 5
153
154config HUDSON_AHCI_ROM
155 bool "Add a AHCI ROM"
156
157config AHCI_ROM_FILE
158 string "AHCI ROM path and filename"
159 depends on HUDSON_AHCI_ROM
Dave Frodinbc21a412015-01-19 11:40:38 -0700160 default "src/southbridge/amd/pi/hudson/ahci.bin"
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300161
162endif
163
164if HUDSON_SATA_MODE = 1
165
166config RAID_ROM_ID
167 string "RAID device PCI IDs"
168 default "1022,7802"
Dave Frodinfedd8e32015-01-21 07:26:26 -0700169 help
170 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300171
172config RAID_ROM_FILE
173 string "RAID ROM path and filename"
Dave Frodinbc21a412015-01-19 11:40:38 -0700174 default "src/southbridge/amd/pi/hudson/raid.bin"
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300175
176config RAID_MISC_ROM_FILE
177 string "RAID Misc ROM path and filename"
Dave Frodinbc21a412015-01-19 11:40:38 -0700178 default "src/southbridge/amd/pi/hudson/misc.bin"
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300179
180config RAID_MISC_ROM_POSITION
181 hex "RAID Misc ROM Position"
182 default 0xFFF00000
183 help
184 The RAID ROM requires that the MISC ROM is located between the range
185 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
186 The CONFIG_ROM_SIZE must be larger than 0x100000.
187
188endif
189
190config HUDSON_LEGACY_FREE
191 bool "System is legacy free"
192 help
193 Select y if there is no keyboard controller in the system.
194 This sets variables in AGESA and ACPI.
195
196config AZ_PIN
197 hex
198 default 0xaa
199 help
200 bit 1,0 - pin 0
201 bit 3,2 - pin 1
202 bit 5,4 - pin 2
203 bit 7,6 - pin 3
Marshall Dawsonc6be0d82017-01-07 18:17:32 -0500204
205config AMDFW_OUTSIDE_CBFS
206 def_bool n
207 help
208 The AMDFW (PSP) is typically locatable in cbfs. Select this
209 option to manually attach the generated amdfw.rom at an
210 offset of 0x20000 from the bottom of the coreboot ROM image.
211
Marc Jones3eec9dd2017-04-09 18:00:40 -0600212config SERIRQ_CONTINUOUS_MODE
213 bool
214 default n
215 help
216 Set this option to y for serial IRQ in continuous mode.
217 Otherwise it is in quiet mode.
Marc Jones7f2c29b2017-04-26 21:55:03 -0600218
219config HUDSON_ACPI_IO_BASE
220 hex
Marc Jones7f2c29b2017-04-26 21:55:03 -0600221 default 0x800
222 help
223 Base address for the ACPI registers.
224 This value must match the hardcoded value of AGESA.
225
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300226endif
Zheng Bao22861382015-11-21 12:19:22 +0800227
228config HUDSON_UART
Zheng Baoe1e9ed32015-12-07 22:59:45 +0800229 bool "UART controller on Kern"
Zheng Bao22861382015-11-21 12:19:22 +0800230 default n
231 depends on SOUTHBRIDGE_AMD_PI_KERN
232 select DRIVERS_UART_8250MEM
233 select DRIVERS_UART_8250MEM_32
234 select NO_UART_ON_SUPERIO
Lee Leahy6ec72c92016-05-07 09:04:46 -0700235 select UART_OVERRIDE_REFCLK
Zheng Bao22861382015-11-21 12:19:22 +0800236 help
237 There are two UART controllers in Kern.
238 The UART registers are memory-mapped. UART
239 controller 0 registers range from FEDC_6000h
240 to FEDC_6FFFh. UART controller 1 registers
241 range from FEDC_8000h to FEDC_8FFFh.