blob: a095fb9f1f1ae5f0ebbea97398ed09977fe21492 [file] [log] [blame]
Lijian Zhao81096042017-05-02 18:54:44 -07001config SOC_INTEL_CANNONLAKE
2 bool
3 help
4 Intel Cannonlake support
5
6if SOC_INTEL_CANNONLAKE
7
8config CPU_SPECIFIC_OPTIONS
9 def_bool y
Lijian Zhaob3dfcb82017-08-16 22:18:52 -070010 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Lijian Zhao0e956f22017-10-22 18:30:39 -070011 select ACPI_NHLT
Lijian Zhao81096042017-05-02 18:54:44 -070012 select ARCH_BOOTBLOCK_X86_32
Lijian Zhao81096042017-05-02 18:54:44 -070013 select ARCH_RAMSTAGE_X86_32
14 select ARCH_ROMSTAGE_X86_32
Lijian Zhaodcf99b02017-07-30 15:40:10 -070015 select ARCH_VERSTAGE_X86_32
Lijian Zhao32111172017-08-16 11:40:03 -070016 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
17 select BOOT_DEVICE_SUPPORTS_WRITES
Lijian Zhao81096042017-05-02 18:54:44 -070018 select C_ENVIRONMENT_BOOTBLOCK
Lijian Zhaoa06f55b2017-10-04 23:08:55 -070019 select CACHE_MRC_SETTINGS
Subrata Banikdc233962018-05-04 13:43:15 +053020 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
Lijian Zhao2b074d92017-08-17 14:25:24 -070021 select COMMON_FADT
Lijian Zhaoacfc1492017-07-06 15:27:27 -070022 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Nick Vaccaro69b5cdb2017-08-29 19:25:23 -070023 select GENERIC_GPIO_LIB
Abhay kumarfcf88202017-09-20 15:17:42 -070024 select HAVE_FSP_GOP
Lijian Zhao81096042017-05-02 18:54:44 -070025 select HAVE_HARD_RESET
26 select HAVE_INTEL_FIRMWARE
Lijian Zhaodcf99b02017-07-30 15:40:10 -070027 select HAVE_MONOTONIC_TIMER
Lijian Zhaof0eb9992017-09-14 14:51:12 -070028 select HAVE_SMI_HANDLER
Abhay Kumarb0c4cbb2017-10-12 11:33:01 -070029 select INTEL_GMA_ACPI
Abhay kumarfcf88202017-09-20 15:17:42 -070030 select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
Lijian Zhaoa5158492017-08-29 14:37:17 -070031 select IOAPIC
Lijian Zhaoa06f55b2017-10-04 23:08:55 -070032 select MRC_SETTINGS_PROTECT
Pratik Prajapati01eda282017-08-17 21:09:45 -070033 select PARALLEL_MP
34 select PARALLEL_MP_AP_WORK
Lijian Zhao81096042017-05-02 18:54:44 -070035 select PLATFORM_USES_FSP2_0
Lijian Zhao8465a812017-07-11 12:33:22 -070036 select POSTCAR_CONSOLE
37 select POSTCAR_STAGE
Lijian Zhaodcf99b02017-07-30 15:40:10 -070038 select REG_SCRIPT
Lijian Zhaof0eb9992017-09-14 14:51:12 -070039 select RELOCATABLE_MODULES
Lijian Zhaoa77c68a2017-07-18 18:14:42 -070040 select RELOCATABLE_RAMSTAGE
Lijian Zhaof0eb9992017-09-14 14:51:12 -070041 select SMM_TSEG
Pratik Prajapati01eda282017-08-17 21:09:45 -070042 select SMP
Subrata Banikac1cd442018-02-06 15:25:27 +053043 select SOC_AHCI_PORT_IMPLEMENTED_INVERT
Lijian Zhao81096042017-05-02 18:54:44 -070044 select SOC_INTEL_COMMON
Lijian Zhao2b074d92017-08-17 14:25:24 -070045 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Lijian Zhao81096042017-05-02 18:54:44 -070046 select SOC_INTEL_COMMON_BLOCK
Lijian Zhao2b074d92017-08-17 14:25:24 -070047 select SOC_INTEL_COMMON_BLOCK_ACPI
Andrey Petrov3e2e0502017-06-05 13:22:24 -070048 select SOC_INTEL_COMMON_BLOCK_CPU
Pratik Prajapati01eda282017-08-17 21:09:45 -070049 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Lijian Zhao81096042017-05-02 18:54:44 -070050 select SOC_INTEL_COMMON_BLOCK_CSE
Lijian Zhao7b2d1ae2017-10-30 14:23:56 -070051 select SOC_INTEL_COMMON_BLOCK_DSP
Subrata Banik47569cf2017-10-12 17:59:02 +053052 select SOC_INTEL_COMMON_BLOCK_EBDA
Lijian Zhaodcf99b02017-07-30 15:40:10 -070053 select SOC_INTEL_COMMON_BLOCK_FAST_SPI
Andrey Petrovc854b492017-06-05 14:10:17 -070054 select SOC_INTEL_COMMON_BLOCK_GPIO
Subrata Banik75c6f4a2017-11-28 18:37:48 +053055 select SOC_INTEL_COMMON_BLOCK_GRAPHICS
Furquan Shaikha5bb7162017-12-20 11:09:04 -080056 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Lijian Zhaoa5158492017-08-29 14:37:17 -070057 select SOC_INTEL_COMMON_BLOCK_ITSS
Lijian Zhao9bb684a2017-10-30 17:03:06 -070058 select SOC_INTEL_COMMON_BLOCK_I2C
Lijian Zhaoa5158492017-08-29 14:37:17 -070059 select SOC_INTEL_COMMON_BLOCK_LPC
Lijian Zhaodcf99b02017-07-30 15:40:10 -070060 select SOC_INTEL_COMMON_BLOCK_LPSS
Lijian Zhao899f5ff2017-10-26 12:02:30 -070061 select SOC_INTEL_COMMON_BLOCK_P2SB
Lijian Zhaodcf99b02017-07-30 15:40:10 -070062 select SOC_INTEL_COMMON_BLOCK_PCR
Lijian Zhaob3dfcb82017-08-16 22:18:52 -070063 select SOC_INTEL_COMMON_BLOCK_PMC
Lijian Zhaodcf99b02017-07-30 15:40:10 -070064 select SOC_INTEL_COMMON_BLOCK_RTC
65 select SOC_INTEL_COMMON_BLOCK_SA
Subrata Banikac1cd442018-02-06 15:25:27 +053066 select SOC_INTEL_COMMON_BLOCK_SATA
Bora Guvendikd2c63652017-09-19 14:04:37 -070067 select SOC_INTEL_COMMON_BLOCK_SCS
Lijian Zhaodcf99b02017-07-30 15:40:10 -070068 select SOC_INTEL_COMMON_BLOCK_SMBUS
Brandon Breitensteinae154862017-08-01 11:32:06 -070069 select SOC_INTEL_COMMON_BLOCK_SMM
70 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banik5a283ef2017-11-07 18:06:36 +053071 select SOC_INTEL_COMMON_BLOCK_SPI
Lijian Zhaodcf99b02017-07-30 15:40:10 -070072 select SOC_INTEL_COMMON_BLOCK_TIMER
73 select SOC_INTEL_COMMON_BLOCK_UART
Duncan Laurie2410cd92018-03-26 02:25:07 -070074 select SOC_INTEL_COMMON_BLOCK_XDCI
Subrata Banik98376b82018-05-22 16:18:16 +053075 select SOC_INTEL_COMMON_BLOCK_XHCI
Lijian Zhao0e956f22017-10-22 18:30:39 -070076 select SOC_INTEL_COMMON_NHLT
Lijian Zhaodcf99b02017-07-30 15:40:10 -070077 select SOC_INTEL_COMMON_RESET
Lijian Zhaof0eb9992017-09-14 14:51:12 -070078 select SSE2
Lijian Zhaoacfc1492017-07-06 15:27:27 -070079 select SUPPORT_CPU_UCODE_IN_CBFS
Lijian Zhaodcf99b02017-07-30 15:40:10 -070080 select TSC_CONSTANT_RATE
81 select TSC_MONOTONIC_TIMER
82 select UDELAY_TSC
Subrata Banik74558812018-01-25 11:41:04 +053083 select UDK_2017_BINDING
Subrata Banika8733e32018-01-23 16:40:56 +053084 select DISPLAY_FSP_VERSION_INFO
Lijian Zhao81096042017-05-02 18:54:44 -070085
86config UART_DEBUG
87 bool "Enable UART debug port."
88 default y
89 select CONSOLE_SERIAL
90 select BOOTBLOCK_CONSOLE
91 select DRIVERS_UART
Lijian Zhaod37ebdd2017-08-30 20:54:16 -070092 select DRIVERS_UART_8250MEM_32
93 select NO_UART_ON_SUPERIO
Lijian Zhao81096042017-05-02 18:54:44 -070094
Subrata Banikce4c9ec2017-08-14 13:23:54 +053095config UART_FOR_CONSOLE
96 int "Index for LPSS UART port to use for console"
Lijian Zhao0c8237a2017-09-14 16:25:18 -070097 default 2 if DRIVERS_UART_8250MEM_32
Subrata Banikb045d4c2017-08-30 11:47:32 +053098 default 0
Subrata Banikce4c9ec2017-08-14 13:23:54 +053099 help
100 Index for LPSS UART port to use for console:
101 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
102
Lijian Zhao81096042017-05-02 18:54:44 -0700103config DCACHE_RAM_BASE
104 default 0xfef00000
105
106config DCACHE_RAM_SIZE
107 default 0x40000
108 help
109 The size of the cache-as-ram region required during bootblock
110 and/or romstage.
111
112config DCACHE_BSP_STACK_SIZE
113 hex
114 default 0x4000
115 help
116 The amount of anticipated stack usage in CAR by bootblock and
117 other stages.
118
Furquan Shaikhc0257dd2018-05-02 23:29:04 -0700119config IFD_CHIPSET
120 string
121 default "cnl"
122
Pratik Prajapati9027e1b2017-08-23 17:37:43 -0700123config IED_REGION_SIZE
124 hex
125 default 0x400000
126
John Zhao7492bcb2018-02-01 15:56:28 -0800127config HEAP_SIZE
128 hex
129 default 0x8000
130
Lijian Zhao0e956f22017-10-22 18:30:39 -0700131config NHLT_DMIC_1CH_16B
132 bool
133 depends on ACPI_NHLT
134 default n
135 help
136 Include DSP firmware settings for 1 channel 16B DMIC array.
137
138config NHLT_DMIC_2CH_16B
139 bool
140 depends on ACPI_NHLT
141 default n
142 help
143 Include DSP firmware settings for 2 channel 16B DMIC array.
144
145config NHLT_DMIC_4CH_16B
146 bool
147 depends on ACPI_NHLT
148 default n
149 help
150 Include DSP firmware settings for 4 channel 16B DMIC array.
151
152config NHLT_MAX98357
153 bool
154 depends on ACPI_NHLT
155 default n
156 help
157 Include DSP firmware settings for headset codec.
158
N, Harshapriya4a1ee4b2017-11-28 14:29:26 -0800159config NHLT_MAX98373
160 bool
161 depends on ACPI_NHLT
162 default n
163 help
164 Include DSP firmware settings for headset codec.
165
Lijian Zhao0e956f22017-10-22 18:30:39 -0700166config NHLT_DA7219
167 bool
168 depends on ACPI_NHLT
169 default n
170 help
171 Include DSP firmware settings for headset codec.
172
Pratik Prajapatic8c741d2017-08-29 11:38:42 -0700173config MAX_ROOT_PORTS
174 int
Lijian Zhaoc85890d2017-10-20 09:19:07 -0700175 default 16
Pratik Prajapatic8c741d2017-08-29 11:38:42 -0700176
Pratik Prajapati9027e1b2017-08-23 17:37:43 -0700177config SMM_TSEG_SIZE
178 hex
179 default 0x800000
180
Subrata Banike66600e2018-05-10 17:23:56 +0530181config SMM_RESERVED_SIZE
182 hex
183 default 0x200000
184
Lijian Zhao81096042017-05-02 18:54:44 -0700185config PCR_BASE_ADDRESS
186 hex
187 default 0xfd000000
188 help
189 This option allows you to select MMIO Base Address of sideband bus.
190
Andrey Petrov3e2e0502017-06-05 13:22:24 -0700191config CPU_BCLK_MHZ
192 int
193 default 100
194
Nick Vaccaro780a1c42017-12-22 22:50:57 -0800195config SOC_INTEL_CANNONLAKE_LPDDR4_INIT
196 bool
197 default n
198
Aaron Durbin551e4be2018-04-10 09:24:54 -0600199config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Lijian Zhaof3885612017-11-09 15:01:33 -0800200 int
201 default 120
202
Chris Chingb8dc63b2017-12-06 14:26:15 -0700203config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
204 int
Lijian Zhaoe09ba472018-04-10 10:33:05 -0700205 default 133
Chris Chingb8dc63b2017-12-06 14:26:15 -0700206
Lijian Zhao32111172017-08-16 11:40:03 -0700207config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
208 int
209 default 3
210
Lijian Zhao8465a812017-07-11 12:33:22 -0700211# Clock divider parameters for 115200 baud rate
212config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
213 hex
214 default 0x30
215
216config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
217 hex
218 default 0xc35
219
Lijian Zhao6d7063c2017-08-29 17:26:48 -0700220config CHROMEOS
221 select CHROMEOS_RAMOOPS_DYNAMIC
222
223config VBOOT
224 select VBOOT_SEPARATE_VERSTAGE
225 select VBOOT_OPROM_MATTERS
226 select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
227 select VBOOT_STARTS_IN_BOOTBLOCK
228 select VBOOT_VBNV_CMOS
229 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
230
Aaron Durbin4a8f45f2017-10-05 17:05:36 -0600231config C_ENV_BOOTBLOCK_SIZE
232 hex
Lijian Zhao031020e2017-12-15 12:58:07 -0800233 default 0x8000
Aaron Durbin4a8f45f2017-10-05 17:05:36 -0600234
Subrata Banik9e3ba212018-01-08 15:28:26 +0530235choice
236 prompt "Cache-as-ram implementation"
237 default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS
238 default USE_CANNONLAKE_FSP_CAR
239 help
240 This option allows you to select how cache-as-ram (CAR) is set up.
241
242config USE_CANNONLAKE_CAR_NEM_ENHANCED
243 bool "Enhanced Non-evict mode"
244 select SOC_INTEL_COMMON_BLOCK_CAR
245 select INTEL_CAR_NEM_ENHANCED
246 help
247 A current limitation of NEM (Non-Evict mode) is that code and data
248 sizes are derived from the requirement to not write out any modified
249 cache line. With NEM, if there is no physical memory behind the
250 cached area, the modified data will be lost and NEM results will be
251 inconsistent. ENHANCED NEM guarantees that modified data is always
252 kept in cache while clean data is replaced.
253
254config USE_CANNONLAKE_FSP_CAR
255 bool "Use FSP CAR"
256 select FSP_CAR
257 help
258 Use FSP APIs to initialize and tear down the Cache-As-Ram.
259
260endchoice
261
Lijian Zhao81096042017-05-02 18:54:44 -0700262endif