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Timothy Pearsond3b2bbe2010-03-01 10:56:51 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000016 */
17
18#include <console/console.h>
19#include <arch/smp/mpspec.h>
20#include <device/pci.h>
21#include <string.h>
22#include <stdint.h>
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000023#include <cpu/amd/amdfam10_sysconf.h>
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000024#include "mb_sysconf.h"
25
Myles Watson08e0fb82010-03-22 16:33:25 +000026static void *smp_write_config_table(void *v)
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000027{
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000028 struct mp_config_table *mc;
29 struct mb_sysconf_t *m;
30 unsigned sbdn;
31
Patrick Georgi5244e1b2010-11-21 14:41:07 +000032 int i, j, bus_isa;
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000033
34 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000035
Patrick Georgic8feedd2012-02-16 18:43:25 +010036 mptable_init(mc, LOCAL_APIC_ADDR);
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000037
38 smp_write_processors(mc);
39
40 get_bus_conf();
41 sbdn = sysconf.sbdn;
42 m = sysconf.mb;
43
Patrick Georgi5244e1b2010-11-21 14:41:07 +000044 mptable_write_buses(mc, NULL, &bus_isa);
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000045
46/*I/O APICs: APIC ID Version State Address*/
47 {
Elyes HAOUAS9740bcb2018-05-04 22:07:08 +020048 struct device *dev;
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000049 struct resource *res;
50 uint32_t dword;
51
52 dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
53 if (dev) {
54 res = find_resource(dev, PCI_BASE_ADDRESS_1);
55 if (res) {
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080056 smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
57 res2mmio(res, 0, 0));
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000058 }
59
60 dword = 0x43c6c643;
61 pci_write_config32(dev, 0x7c, dword);
62
63 dword = 0x81001a00;
64 pci_write_config32(dev, 0x80, dword);
65
66 dword = 0xd00012d2;
67 pci_write_config32(dev, 0x84, dword);
68
69 }
70
71
72 }
73
Patrick Georgi5244e1b2010-11-21 14:41:07 +000074 mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000075
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
77
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
79
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
81
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
83
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
87
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
90
Elyes HAOUAS7533e492018-02-01 09:35:53 +010091 for (j = 7; j >= 2; j--) {
92 if (!m->bus_mcp55[j])
93 continue;
94 for (i = 0; i < 4; i++)
Elyes HAOUASa5aad2e2016-09-19 09:47:16 -060095 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +000096 }
97
Elyes HAOUAS7533e492018-02-01 09:35:53 +010098 for (j = 0; j < 1; j++)
99 for (i = 0; i < 4; i++)
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +0000100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +0000101
102/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
Patrick Georgi6eb7a532011-10-07 21:42:52 +0200103 mptable_lintsrc(mc, bus_isa);
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +0000104 /* There is no extension information... */
105
106 /* Compute the checksums */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200107 return mptable_finalize(mc);
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +0000108}
109
110unsigned long write_smp_table(unsigned long addr)
111{
112 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200113 v = smp_write_floating_table(addr, 0);
Timothy Pearsond3b2bbe2010-03-01 10:56:51 +0000114 return (unsigned long)smp_write_config_table(v);
115}