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Myles Watson707fad02009-10-23 18:22:27 +00001/*
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +00002 * This file is part of the coreboot project.
Myles Watson707fad02009-10-23 18:22:27 +00003 *
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +00004 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2005 Eswar Nallusamy, LANL
6 * Copyright (C) 2005 Tyan
7 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
8 * Copyright (C) 2007 coresystems GmbH
9 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
10 * Copyright (C) 2007,2008 Carl-Daniel Hailfinger
11 * Copyright (C) 2008 VIA Technologies, Inc.
12 * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
Myles Watson707fad02009-10-23 18:22:27 +000013 *
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000014 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; version 2 of the License.
Myles Watson707fad02009-10-23 18:22:27 +000017 *
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000018 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000022 */
23
Myles Watson707fad02009-10-23 18:22:27 +000024#include <cpu/x86/mtrr.h>
Patrick Georgi05e740f2012-03-31 12:52:21 +020025#include <cpu/x86/cache.h>
Alexandru Gagniuc5005bb02011-04-11 20:17:22 +000026#include <console/post_codes.h>
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000027
Uwe Hermann42926842010-09-30 23:15:36 +000028#define CacheSize CONFIG_DCACHE_RAM_SIZE
29#define CacheBase CONFIG_DCACHE_RAM_BASE
30
Stefan Reinauer7b0500c2011-01-19 06:54:42 +000031 /* Save the BIST result. */
32 movl %eax, %ebp
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000033
34CacheAsRam:
35
Stefan Reinauer7b0500c2011-01-19 06:54:42 +000036 /* Disable cache. */
37 movl %cr0, %eax
Patrick Georgi05e740f2012-03-31 12:52:21 +020038 orl $CR0_CacheDisable, %eax
Stefan Reinauer7b0500c2011-01-19 06:54:42 +000039 movl %eax, %cr0
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000040 invd
41
Uwe Hermann42926842010-09-30 23:15:36 +000042 /* Set the default memory type and enable fixed and variable MTRRs. */
Alexandru Gagniuc86091f92015-09-30 20:23:09 -070043 movl $MTRR_DEF_TYPE_MSR, %ecx
Myles Watson707fad02009-10-23 18:22:27 +000044 xorl %edx, %edx
Alexandru Gagniuc86091f92015-09-30 20:23:09 -070045 movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000046 wrmsr
47
Uwe Hermann42926842010-09-30 23:15:36 +000048 /* Clear all MTRRs. */
Myles Watson707fad02009-10-23 18:22:27 +000049 xorl %edx, %edx
Warren Turkal4ffde942010-10-12 06:13:40 +000050 movl $all_mtrr_msrs, %esi
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000051
Myles Watson707fad02009-10-23 18:22:27 +000052clear_fixed_var_mtrr:
53 lodsl (%esi), %eax
54 testl %eax, %eax
55 jz clear_fixed_var_mtrr_out
56
57 movl %eax, %ecx
58 xorl %eax, %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000059 wrmsr
60
Myles Watson707fad02009-10-23 18:22:27 +000061 jmp clear_fixed_var_mtrr
Stefan Reinauer314e5512010-04-09 20:36:29 +000062
Warren Turkal4ffde942010-10-12 06:13:40 +000063all_mtrr_msrs:
64 /* fixed MTRR MSRs */
Alexandru Gagniuc86091f92015-09-30 20:23:09 -070065 .long MTRR_FIX_64K_00000
66 .long MTRR_FIX_16K_80000
67 .long MTRR_FIX_16K_A0000
68 .long MTRR_FIX_4K_C0000
69 .long MTRR_FIX_4K_C8000
70 .long MTRR_FIX_4K_D0000
71 .long MTRR_FIX_4K_D8000
72 .long MTRR_FIX_4K_E0000
73 .long MTRR_FIX_4K_E8000
74 .long MTRR_FIX_4K_F0000
75 .long MTRR_FIX_4K_F8000
Stefan Reinauer314e5512010-04-09 20:36:29 +000076
Warren Turkal4ffde942010-10-12 06:13:40 +000077 /* var MTRR MSRs */
Alexandru Gagniuc86091f92015-09-30 20:23:09 -070078 .long MTRR_PHYS_BASE(0)
79 .long MTRR_PHYS_MASK(0)
80 .long MTRR_PHYS_BASE(1)
81 .long MTRR_PHYS_MASK(1)
82 .long MTRR_PHYS_BASE(2)
83 .long MTRR_PHYS_MASK(2)
84 .long MTRR_PHYS_BASE(3)
85 .long MTRR_PHYS_MASK(3)
86 .long MTRR_PHYS_BASE(4)
87 .long MTRR_PHYS_MASK(4)
88 .long MTRR_PHYS_BASE(5)
89 .long MTRR_PHYS_MASK(5)
90 .long MTRR_PHYS_BASE(6)
91 .long MTRR_PHYS_MASK(6)
92 .long MTRR_PHYS_BASE(7)
93 .long MTRR_PHYS_MASK(7)
Warren Turkal4ffde942010-10-12 06:13:40 +000094
Stefan Reinauer314e5512010-04-09 20:36:29 +000095 .long 0x000 /* NULL, end of table */
96
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000097clear_fixed_var_mtrr_out:
Alexandru Gagniuc86091f92015-09-30 20:23:09 -070098 movl $MTRR_PHYS_BASE(0), %ecx
Myles Watson707fad02009-10-23 18:22:27 +000099 xorl %edx, %edx
Uwe Hermann42926842010-09-30 23:15:36 +0000100 movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000101 wrmsr
102
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700103 movl $MTRR_PHYS_MASK(0), %ecx
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000104 /* This assumes we never access addresses above 2^36 in CAR. */
Uwe Hermann42926842010-09-30 23:15:36 +0000105 movl $0x0000000f, %edx
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700106 movl $(~(CacheSize - 1) | MTRR_PHYS_MASK_VALID), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000107 wrmsr
108
Uwe Hermann42926842010-09-30 23:15:36 +0000109 /*
110 * Enable write base caching so we can do execute in place (XIP)
111 * on the flash ROM.
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000112 */
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700113 movl $MTRR_PHYS_BASE(1), %ecx
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000114 xorl %edx, %edx
Uwe Hermann36455aa2010-10-02 20:51:29 +0000115 /*
Patrick Georgi1da10462011-10-28 20:28:03 +0200116 * IMPORTANT: The following calculation _must_ be done at runtime. See
Paul Menzela8843de2017-06-05 12:33:23 +0200117 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
Uwe Hermann36455aa2010-10-02 20:51:29 +0000118 */
Rudolf Marek9438da32011-10-30 18:06:58 +0100119 movl $copy_and_run, %eax
Patrick Georgi1da10462011-10-28 20:28:03 +0200120 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
Stefan Reinauerf11b81d2010-10-01 12:24:57 +0000121 orl $MTRR_TYPE_WRBACK, %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000122 wrmsr
123
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700124 movl $MTRR_PHYS_MASK(1), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000125 movl $0x0000000f, %edx
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700126 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000127 wrmsr
128
Uwe Hermann66d16872010-10-01 07:27:51 +0000129 /* Set the default memory type and enable fixed and variable MTRRs. */
130 /* TODO: Or also enable fixed MTRRs? Bug in the code? */
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700131 movl $MTRR_DEF_TYPE_MSR, %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000132 xorl %edx, %edx
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700133 movl $(MTRR_DEF_TYPE_EN), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000134 wrmsr
135
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000136 /* Enable cache. */
137 movl %cr0, %eax
Patrick Georgi05e740f2012-03-31 12:52:21 +0200138 andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000139 movl %eax, %cr0
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000140
Uwe Hermann42926842010-09-30 23:15:36 +0000141 /* Read the range with lodsl. */
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000142 cld
Myles Watson707fad02009-10-23 18:22:27 +0000143 movl $CacheBase, %esi
144 movl %esi, %edi
Uwe Hermann42926842010-09-30 23:15:36 +0000145 movl $(CacheSize >> 2), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000146 rep lodsl
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000147
Myles Watson707fad02009-10-23 18:22:27 +0000148 movl $CacheBase, %esi
149 movl %esi, %edi
150 movl $(CacheSize >> 2), %ecx
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000151
Lubomir Rintel9618cf42018-01-01 14:36:49 +0100152 /* Zero out the cache-as-ram area. */
153 xorl %eax, %eax
Myles Watson707fad02009-10-23 18:22:27 +0000154 rep stosl
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000155
Uwe Hermann42926842010-09-30 23:15:36 +0000156 /*
157 * The key point of this CAR code is C7 cache does not turn into
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000158 * "no fill" mode, which is not compatible with general CAR code.
159 */
160
Myles Watson707fad02009-10-23 18:22:27 +0000161 movl $(CacheBase + CacheSize - 4), %eax
162 movl %eax, %esp
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000163
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000164 /* Restore the BIST result. */
165 movl %ebp, %eax
Myles Watson707fad02009-10-23 18:22:27 +0000166
Uwe Hermann42926842010-09-30 23:15:36 +0000167 /* We need to set EBP? No need. */
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000168 movl %esp, %ebp
Uwe Hermann42926842010-09-30 23:15:36 +0000169 pushl %eax /* BIST */
Stefan Reinauer314e5512010-04-09 20:36:29 +0000170 call main
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000171
Stefan Reinauer14e22772010-04-27 06:56:47 +0000172 /*
Stefan Reinauer314e5512010-04-09 20:36:29 +0000173 * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
174 * get STACK up, we restore that. It is only needed if we
175 * want to go back.
176 */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000177
Uwe Hermann66d16872010-10-01 07:27:51 +0000178 /* We don't need CAR from now on. */
Stefan Reinauer314e5512010-04-09 20:36:29 +0000179
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000180 /* Disable cache. */
181 movl %cr0, %eax
Patrick Georgi05e740f2012-03-31 12:52:21 +0200182 orl $CR0_CacheDisable, %eax
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000183 movl %eax, %cr0
Stefan Reinauer314e5512010-04-09 20:36:29 +0000184
Uwe Hermann66d16872010-10-01 07:27:51 +0000185 /* Set the default memory type and enable variable MTRRs. */
186 /* TODO: Or also enable fixed MTRRs? Bug in the code? */
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700187 movl $MTRR_DEF_TYPE_MSR, %ecx
Uwe Hermann42926842010-09-30 23:15:36 +0000188 xorl %edx, %edx
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700189 movl $(MTRR_DEF_TYPE_EN), %eax
Stefan Reinauer314e5512010-04-09 20:36:29 +0000190 wrmsr
191
Kyösti Mälkki65cc5262016-06-19 20:38:41 +0300192 /* Enable caching for 0..CACHE_TMP_RAMTOP. */
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700193 movl $MTRR_PHYS_BASE(0), %ecx
Uwe Hermann42926842010-09-30 23:15:36 +0000194 xorl %edx, %edx
Kyösti Mälkkid71cfd22016-06-16 21:14:25 +0300195 movl $(0x0 | MTRR_TYPE_WRBACK), %eax
Stefan Reinauer314e5512010-04-09 20:36:29 +0000196 wrmsr
Stefan Reinauer14e22772010-04-27 06:56:47 +0000197
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700198 movl $MTRR_PHYS_MASK(0), %ecx
Uwe Hermann42926842010-09-30 23:15:36 +0000199 movl $0x0000000f, %edx /* AMD 40 bit 0xff */
Kyösti Mälkki65cc5262016-06-19 20:38:41 +0300200 movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
Stefan Reinauer14e22772010-04-27 06:56:47 +0000201 wrmsr
202
Patrick Georgi784544b2011-10-31 17:07:52 +0100203 /* Cache XIP_ROM area to speedup coreboot code. */
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700204 movl $MTRR_PHYS_BASE(1), %ecx
Uwe Hermann42926842010-09-30 23:15:36 +0000205 xorl %edx, %edx
Patrick Georgi1da10462011-10-28 20:28:03 +0200206 /*
207 * IMPORTANT: The following calculation _must_ be done at runtime. See
Paul Menzela8843de2017-06-05 12:33:23 +0200208 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
Patrick Georgi1da10462011-10-28 20:28:03 +0200209 */
Rudolf Marek9438da32011-10-30 18:06:58 +0100210 movl $copy_and_run, %eax
Patrick Georgi1da10462011-10-28 20:28:03 +0200211 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
Stefan Reinauerf11b81d2010-10-01 12:24:57 +0000212 orl $MTRR_TYPE_WRBACK, %eax
Stefan Reinauer314e5512010-04-09 20:36:29 +0000213 wrmsr
214
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700215 movl $MTRR_PHYS_MASK(1), %ecx
Uwe Hermann42926842010-09-30 23:15:36 +0000216 xorl %edx, %edx
Alexandru Gagniuc86091f92015-09-30 20:23:09 -0700217 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
Stefan Reinauer314e5512010-04-09 20:36:29 +0000218 wrmsr
219
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000220 /* Enable cache. */
221 movl %cr0, %eax
Patrick Georgi05e740f2012-03-31 12:52:21 +0200222 andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000223 movl %eax, %cr0
Stefan Reinauer314e5512010-04-09 20:36:29 +0000224 invd
225
Stefan Reinauer314e5512010-04-09 20:36:29 +0000226__main:
Alexandru Gagniuc5005bb02011-04-11 20:17:22 +0000227 post_code(POST_PREPARE_RAMSTAGE)
Uwe Hermann42926842010-09-30 23:15:36 +0000228 cld /* Clear direction flag. */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000229
Kyösti Mälkki1729cd82014-10-16 12:47:25 +0300230 movl $CONFIG_RAMTOP, %esp
Stefan Reinauer314e5512010-04-09 20:36:29 +0000231 movl %esp, %ebp
Uwe Hermann42926842010-09-30 23:15:36 +0000232 call copy_and_run
Stefan Reinauer314e5512010-04-09 20:36:29 +0000233
Stefan Reinauer14e22772010-04-27 06:56:47 +0000234.Lhlt:
Alexandru Gagniuc5005bb02011-04-11 20:17:22 +0000235 post_code(POST_DEAD_CODE)
Stefan Reinauer314e5512010-04-09 20:36:29 +0000236 hlt
237 jmp .Lhlt