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Thaminda Edirisooriyab0945832015-08-26 15:28:04 -07001/*
2 * Early initialization code for riscv virtual memory
3 *
4 * Copyright 2015 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
14 * GNU General Public License for more details.
Thaminda Edirisooriyab0945832015-08-26 15:28:04 -070015 */
16
Thaminda Edirisooriyab0945832015-08-26 15:28:04 -070017#include <arch/encoding.h>
Jonathan Neuschäfercc5be8b2016-07-26 01:54:34 +020018#include <stdint.h>
19#include <vm.h>
Thaminda Edirisooriyab0945832015-08-26 15:28:04 -070020
Ronald G. Minnich3d302b02016-11-12 07:31:16 -080021/* Delegate controls which traps are delegated to the payload. If you
22 * wish to temporarily disable some or all delegation you can, in a
23 * debugger, set it to a different value (e.g. 0 to have all traps go
24 * to M-mode). In practice, this variable has been a lifesaver. It is
25 * still not quite determined which delegation might by unallowed by
26 * the spec so for now we enumerate and set them all. */
27static int delegate = 0
28 | (1 << CAUSE_MISALIGNED_FETCH)
Jonathan Neuschäfera5c49b82018-02-16 13:36:46 +010029 | (1 << CAUSE_FETCH_ACCESS)
Ronald G. Minnich3d302b02016-11-12 07:31:16 -080030 | (1 << CAUSE_ILLEGAL_INSTRUCTION)
31 | (1 << CAUSE_BREAKPOINT)
Jonathan Neuschäfera5c49b82018-02-16 13:36:46 +010032 | (1 << CAUSE_LOAD_ACCESS)
33 | (1 << CAUSE_STORE_ACCESS)
Ronald G. Minnich3d302b02016-11-12 07:31:16 -080034 | (1 << CAUSE_USER_ECALL)
Jonathan Neuschäfer61864142018-02-16 13:36:46 +010035 | (1 << CAUSE_FETCH_PAGE_FAULT)
36 | (1 << CAUSE_LOAD_PAGE_FAULT)
37 | (1 << CAUSE_STORE_PAGE_FAULT)
Ronald G. Minnich3d302b02016-11-12 07:31:16 -080038 ;
Ronald G. Minnich4e793ec2016-11-04 11:27:25 -070039
Thaminda Edirisooriyab0945832015-08-26 15:28:04 -070040void mstatus_init(void)
41{
Thaminda Edirisooriyab0945832015-08-26 15:28:04 -070042 uintptr_t ms = 0;
Ronald G. Minnichd9307c22016-12-12 15:09:42 -080043
Thaminda Edirisooriyab0945832015-08-26 15:28:04 -070044 ms = INSERT_FIELD(ms, MSTATUS_FS, 3);
45 ms = INSERT_FIELD(ms, MSTATUS_XS, 3);
46 write_csr(mstatus, ms);
Thaminda Edirisooriyab0945832015-08-26 15:28:04 -070047
Ronald G. Minnichd9307c22016-12-12 15:09:42 -080048 // clear any pending timer interrupts.
49 clear_csr(mip, MIP_STIP | MIP_SSIP);
50
51 // enable machine and supervisor timer and
52 // all other supervisor interrupts.
53 set_csr(mie, MIP_MTIP | MIP_STIP | MIP_SSIP);
54
55 // Delegate supervisor timer and other interrupts
56 // to supervisor mode.
57 set_csr(mideleg, MIP_STIP | MIP_SSIP);
Jonathan Neuschäferd9ff75f2016-08-22 19:37:15 +020058
Ronald G. Minnich3d302b02016-11-12 07:31:16 -080059 set_csr(medeleg, delegate);
Ronald G. Minnich5965cba2016-10-19 08:07:13 -070060
Ronald G. Minnichf171e662016-12-19 09:06:00 -080061 // Enable all user/supervisor-mode counters using
wxjstzd2779602017-06-06 16:50:46 +080062 // v1.10 register addresses.
Ronald G. Minnichf171e662016-12-19 09:06:00 -080063 // They moved from the earlier spec.
64 // Until we trust our toolchain use the hardcoded constants.
65 // These were in flux and people who get the older toolchain
66 // will have difficult-to-debug failures.
wxjstzd2779602017-06-06 16:50:46 +080067 write_csr(/*mcounteren*/0x306, 7);
Thaminda Edirisooriyab0945832015-08-26 15:28:04 -070068}