blob: 2513c50030b7d3a4aff4881aaa5cb7ae65ff2aa4 [file] [log] [blame]
Stefan Reinauera48ca842015-04-04 01:58:28 +02001config ARCH_RISCV
2 bool
3 default n
4
Jonathan Neuschäfer27649192018-02-13 14:01:22 +01005config ARCH_RISCV_COMPRESSED
6 bool
7 default n
8 help
9 Enable this option if your RISC-V processor supports compressed
10 instructions (RVC). Currently, this enables RVC for all stages.
11
Ronald G. Minniche0e784a2014-11-26 19:25:47 +000012config ARCH_BOOTBLOCK_RISCV
13 bool
14 default n
15 select ARCH_RISCV
Alexandru Gagniucee464b12015-10-02 18:01:18 -070016 select C_ENVIRONMENT_BOOTBLOCK
Ronald G. Minniche0e784a2014-11-26 19:25:47 +000017
Stefan Reinauer77b16552015-01-14 19:51:47 +010018config ARCH_VERSTAGE_RISCV
19 bool
20 default n
21
Ronald G. Minniche0e784a2014-11-26 19:25:47 +000022config ARCH_ROMSTAGE_RISCV
23 bool
24 default n
25
26config ARCH_RAMSTAGE_RISCV
27 bool
28 default n