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review.coreboot.org / coreboot / 961a7b0c08e73e8a7d0061caaef842f1584335fb / . / src / cpu / Kconfig
blob: 1b72f6e5aaaec20c81b48aea95aa4f227bd08a23 [file] [log] [blame]
Ronald G. Minnich5f6572e2009-08-12 15:39:38 +0000[diff] [blame]1source src/cpu/amd/Kconfig
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]2source src/cpu/intel/Kconfig
3source src/cpu/via/Kconfig
4source src/cpu/x86/Kconfig
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]5
Patrick Georgi39ec29c2009-08-27 12:10:50 +0000[diff] [blame]6config USE_DCACHE_RAM
7 bool
Stefan Reinauer314e5512010-04-09 20:36:29 +0000[diff] [blame]8 default !ROMCC
Patrick Georgi39ec29c2009-08-27 12:10:50 +0000[diff] [blame]9
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]10config DCACHE_RAM_BASE
11 hex
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]12
13config DCACHE_RAM_SIZE
14 hex
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]15
Patrick Georgi88f55b22009-09-25 18:43:02 +0000[diff] [blame]16config DCACHE_RAM_GLOBAL_VAR_SIZE
17 hex
Uwe Hermann748475b2009-10-09 11:47:21 +0000[diff] [blame]18 default 0x0
Patrick Georgi88f55b22009-09-25 18:43:02 +0000[diff] [blame]19
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]20config MAX_PHYSICAL_CPUS
21 int
22 default 1
23
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]24config SMP
25 bool
Myles Watson45bb25f2009-09-22 18:49:08 +0000[diff] [blame]26 default y if MAX_CPUS != 1
Patrick Georgi892b0912009-09-24 09:03:06 +0000[diff] [blame]27 default n
Uwe Hermanna29ad5c2009-10-18 18:35:50 +0000[diff] [blame]28 help
29 This option is used to enable certain functions to make coreboot
30 work correctly on symmetric multi processor (SMP) systems.
Ronald G. Minnich149d6752009-10-01 23:22:50 +0000[diff] [blame]31
32config MMX
33 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +0000[diff] [blame]34 help
35 Select MMX in your socket or model Kconfig if your CPU has MMX
36 streaming SIMD instructions. ROMCC can build more efficient
37 code if it can spill to MMX registers.
Ronald G. Minnich149d6752009-10-01 23:22:50 +0000[diff] [blame]38
39config SSE
40 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +0000[diff] [blame]41 help
42 Select SSE in your socket or model Kconfig if your CPU has SSE
43 streaming SIMD instructions. ROMCC can build more efficient
44 code if it can spill to SSE (aka XMM) registers.
45
46config SSE2
47 bool
Myles Watson34261952010-03-19 02:33:40 +0000[diff] [blame]48 default n
Stefan Reinauera7acc512010-02-25 13:40:49 +0000[diff] [blame]49 help
50 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
51 streaming SIMD instructions. Some parts of coreboot can be built
52 with more efficient code if SSE2 instructions are available.
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]53
54config VAR_MTRR_HOLE
55 bool
56 default y
57 help
58 Unset this if you don't want the MTRR code to use
59 subtractive MTRRs