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Gabe Blackd3163ab2013-05-16 05:53:40 -07001/*
2 * This file is part of the coreboot project.
3 *
David Hendricks1e3e2c52013-06-14 16:08:05 -07004 * Copyright 2013 Google Inc.
Gabe Blackd3163ab2013-05-16 05:53:40 -07005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <types.h>
David Hendricks1e3e2c52013-06-14 16:08:05 -070021#include <stdlib.h>
Gabe Blackd3163ab2013-05-16 05:53:40 -070022
23#include <armv7.h>
24#include <cbfs.h>
25
26#include <arch/cache.h>
27#include <cpu/samsung/exynos5420/i2c.h>
28#include <cpu/samsung/exynos5420/clk.h>
29#include <cpu/samsung/exynos5420/cpu.h>
30#include <cpu/samsung/exynos5420/dmc.h>
31#include <cpu/samsung/exynos5420/gpio.h>
32#include <cpu/samsung/exynos5420/setup.h>
33#include <cpu/samsung/exynos5420/periph.h>
34#include <cpu/samsung/exynos5420/power.h>
35#include <cpu/samsung/exynos5420/wakeup.h>
36#include <console/console.h>
37#include <arch/stages.h>
38
David Hendricks1e3e2c52013-06-14 16:08:05 -070039#include <drivers/maxim/max77802/max77802.h>
Gabe Blackd3163ab2013-05-16 05:53:40 -070040#include <device/i2c.h>
41
42#include "exynos5420.h"
43
Gabe Blackd3163ab2013-05-16 05:53:40 -070044#define MMC0_GPIO_PIN (58)
45
David Hendricks1e3e2c52013-06-14 16:08:05 -070046struct pmic_write
47{
48 int or_orig; // Whether to or in the original value.
49 uint8_t reg; // Register to write.
50 uint8_t val; // Value to write.
51};
52
53/*
54 * Use read-modify-write for MAX77802 control registers and clobber the
55 * output voltage setting (BUCK?DVS?) registers.
56 */
57struct pmic_write pmic_writes[] =
58{
59 { 1, MAX77802_REG_PMIC_32KHZ, MAX77802_32KHCP_EN },
60 { 0, MAX77802_REG_PMIC_BUCK1DVS1, MAX77802_BUCK1DVS1_1V },
61 { 1, MAX77802_REG_PMIC_BUCK1CTRL, MAX77802_BUCK_TYPE1_ON |
62 MAX77802_BUCK_TYPE1_IGNORE_PWRREQ },
63 { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1V },
64 { 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON |
65 MAX77802_BUCK_TYPE2_IGNORE_PWRREQ },
66 { 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V },
67 { 1, MAX77802_REG_PMIC_BUCK3CTRL1, MAX77802_BUCK_TYPE2_ON |
68 MAX77802_BUCK_TYPE2_IGNORE_PWRREQ },
69 { 0, MAX77802_REG_PMIC_BUCK4DVS1, MAX77802_BUCK4DVS1_1V },
70 { 1, MAX77802_REG_PMIC_BUCK4CTRL1, MAX77802_BUCK_TYPE2_ON |
71 MAX77802_BUCK_TYPE2_IGNORE_PWRREQ },
72 { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V },
73 { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON |
Ronald G. Minnich88ac9b52013-06-26 17:28:52 -070074 MAX77802_BUCK_TYPE1_IGNORE_PWRREQ },
75 { 1, MAX77802_REG_PMIC_LDO35CTRL1, MAX77802_LDO35CTRL1_1_2V },
David Hendricks1e3e2c52013-06-14 16:08:05 -070076};
77
Hung-Te Linda7b8e42013-06-28 17:27:17 +080078static void setup_power(int is_resume)
Gabe Blackd3163ab2013-05-16 05:53:40 -070079{
80 int error = 0;
David Hendricks1e3e2c52013-06-14 16:08:05 -070081 int i;
Gabe Blackd3163ab2013-05-16 05:53:40 -070082
83 power_init();
84
Hung-Te Linda7b8e42013-06-28 17:27:17 +080085 if (is_resume) {
86 return;
87 }
88
Gabe Blackd3163ab2013-05-16 05:53:40 -070089 /* Initialize I2C bus to configure PMIC. */
David Hendricks1e3e2c52013-06-14 16:08:05 -070090 exynos_pinmux_i2c4();
91 i2c_init(4, I2C_4_SPEED, 0x00);
Gabe Blackd3163ab2013-05-16 05:53:40 -070092
93 printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__);
Gabe Blackd3163ab2013-05-16 05:53:40 -070094
David Hendricks1e3e2c52013-06-14 16:08:05 -070095 for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) {
96 uint8_t data = 0;
97 uint8_t reg = pmic_writes[i].reg;
Gabe Blackd3163ab2013-05-16 05:53:40 -070098
David Hendricks1e3e2c52013-06-14 16:08:05 -070099 if (pmic_writes[i].or_orig)
100 error |= i2c_read(4, MAX77802_I2C_ADDR,
101 reg, sizeof(reg),
102 &data, sizeof(data));
103 data |= pmic_writes[i].val;
104 error |= i2c_write(4, MAX77802_I2C_ADDR,
105 reg, sizeof(reg),
106 &data, sizeof(data));
Gabe Blackd3163ab2013-05-16 05:53:40 -0700107 }
David Hendricks1e3e2c52013-06-14 16:08:05 -0700108
109 if (error)
110 die("Failed to intialize PMIC.\n");
Gabe Blackd3163ab2013-05-16 05:53:40 -0700111}
112
113static void setup_storage(void)
114{
115 /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
116 if (clock_set_mshci(PERIPH_ID_SDMMC0))
117 printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
118 if (gpio_direction_output(MMC0_GPIO_PIN, 1)) {
119 printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__);
120 }
121 gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE);
122 gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X);
Gabe Blacke6a44eb2013-06-15 23:40:26 -0700123 exynos_pinmux_sdmmc0();
Gabe Blackd3163ab2013-05-16 05:53:40 -0700124
125 /* MMC2: Removable, 4 bit mode, no GPIO. */
126 clock_set_mshci(PERIPH_ID_SDMMC2);
Gabe Blacke6a44eb2013-06-15 23:40:26 -0700127 exynos_pinmux_sdmmc2();
Gabe Blackd3163ab2013-05-16 05:53:40 -0700128}
129
Hung-Te Linc357aed2013-06-24 20:02:01 +0800130static void setup_ec(void)
131{
132 /* SPI2 (EC) is slower and needs to work in half-duplex mode with
133 * single byte bus width. */
134 clock_set_rate(PERIPH_ID_SPI2, 500000);
135 exynos_pinmux_spi2();
136}
137
Gabe Blackd3163ab2013-05-16 05:53:40 -0700138static void setup_gpio(void)
139{
Gabe Black63bb6102013-06-19 03:29:45 -0700140 gpio_direction_input(GPIO_X30); // WP_GPIO
141 gpio_set_pull(GPIO_X30, GPIO_PULL_NONE);
Gabe Blackd3163ab2013-05-16 05:53:40 -0700142
Gabe Black63bb6102013-06-19 03:29:45 -0700143 gpio_direction_input(GPIO_X07); // RECMODE_GPIO
144 gpio_set_pull(GPIO_X07, GPIO_PULL_NONE);
Gabe Blackd3163ab2013-05-16 05:53:40 -0700145
Gabe Black63bb6102013-06-19 03:29:45 -0700146 gpio_direction_input(GPIO_X34); // LID_GPIO
147 gpio_set_pull(GPIO_X34, GPIO_PULL_NONE);
Gabe Blackd3163ab2013-05-16 05:53:40 -0700148
Gabe Black63bb6102013-06-19 03:29:45 -0700149 gpio_direction_input(GPIO_X12); // POWER_GPIO
150 gpio_set_pull(GPIO_X12, GPIO_PULL_NONE);
Gabe Blackd3163ab2013-05-16 05:53:40 -0700151}
152
153static void setup_memory(struct mem_timings *mem, int is_resume)
154{
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700155 printk(BIOS_SPEW, "manufacturer: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n",
Gabe Blackd3163ab2013-05-16 05:53:40 -0700156 mem->mem_manuf,
157 mem->mem_type,
158 mem->mpll_mdiv,
159 mem->frequency_mhz);
160
161 /* FIXME Currently memory initialization with mem_reset on normal boot
162 * will cause resume to fail (even if we don't do mem_reset on resume),
163 * and the workaround is to temporarily always enable "is_resume".
164 * This should be removed when the root cause of resume issue is found.
165 */
166 is_resume = 1;
167
168 if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) {
169 die("Failed to initialize memory controller.\n");
170 }
171}
172
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700173#define PRIMITIVE_MEM_TEST 0
174#if PRIMITIVE_MEM_TEST
175static unsigned long primitive_mem_test(void)
Gabe Blackd3163ab2013-05-16 05:53:40 -0700176{
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700177 unsigned long *l = (void *)0x40000000;
178 int bad = 0;
179 unsigned long i;
180 for(i = 0; i < 256*1048576; i++){
181 if (! (i%1048576))
182 printk(BIOS_SPEW, "%lu ...", i);
183 l[i] = 0xffffffff - i;
Gabe Blackd3163ab2013-05-16 05:53:40 -0700184 }
Gabe Black5420e092013-05-17 11:29:22 -0700185
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700186 for(i = 0; i < 256*1048576; i++){
187 if (! (i%1048576))
188 printk(BIOS_SPEW, "%lu ...", i);
189 if (l[i] != (0xffffffff - i)){
190 printk(BIOS_SPEW, "%p: want %08lx got %08lx\n", l, l[i], 0xffffffff - i);
191 bad++;
192 }
193 }
Gabe Black5420e092013-05-17 11:29:22 -0700194
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700195 printk(BIOS_SPEW, "%d errors\n", bad);
196
197 return bad;
Gabe Blackd3163ab2013-05-16 05:53:40 -0700198}
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700199#else
200#define primitive_mem_test()
201#endif
202
203#define SIMPLE_SPI_TEST 0
204#if SIMPLE_SPI_TEST
205/* here is a simple SPI debug test, known to fid trouble */
206static void simple_spi_test(void)
207{
208 struct cbfs_media default_media, *media;
209 int i, amt = 4 * MiB, errors = 0;
210 //u32 *data = (void *)0x40000000;
211 u32 data[1024];
212 u32 in;
213
214 amt = sizeof(data);
215 media = &default_media;
216 if (init_default_cbfs_media(media) != 0) {
217 printk(BIOS_SPEW, "Failed to initialize default media.\n");
218 return;
219 }
220
221
222 media->open(media);
223 if (media->read(media, data, (size_t) 0, amt) < amt){
224 printk(BIOS_SPEW, "simple_spi_test fails\n");
225 return;
226 }
227
228
229 for(i = 0; i < amt; i += 4){
230 if (media->read(media, &in, (size_t) i, 4) < 1){
231 printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i);
232 return;
233 }
234 if (data[i/4] != in){
235 errors++;
236 printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n",
237 i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in);
238 /* reread it to see which is wrong. */
239 if (media->read(media, &in, (size_t) i, 4) < 1){
240 printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i);
241 return;
242 }
243 printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n",
244 i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in);
245 }
246
247 }
248 printk(BIOS_SPEW, "%d errors\n", errors);
249}
250#else
251#define simple_spi_test()
252#endif
Gabe Blackd3163ab2013-05-16 05:53:40 -0700253
254void main(void)
255{
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700256
257 extern struct mem_timings mem_timings;
Gabe Blackd3163ab2013-05-16 05:53:40 -0700258 void *entry;
259 int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
260
261 /* Clock must be initialized before console_init, otherwise you may need
262 * to re-initialize serial console drivers again. */
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700263 system_clock_init();
Gabe Blackd3163ab2013-05-16 05:53:40 -0700264
Stefan Reinauer998ab0d2013-05-20 12:29:37 -0700265 console_init();
266
Hung-Te Linda7b8e42013-06-28 17:27:17 +0800267 setup_power(is_resume);
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700268 setup_memory(&mem_timings, is_resume);
269
270 primitive_mem_test();
Gabe Blackd3163ab2013-05-16 05:53:40 -0700271
272 if (is_resume) {
273 wakeup();
274 }
275
276 setup_storage();
277 setup_gpio();
Hung-Te Linc357aed2013-06-24 20:02:01 +0800278 setup_ec();
Gabe Blackd3163ab2013-05-16 05:53:40 -0700279
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700280 simple_spi_test();
Gabe Blackd3163ab2013-05-16 05:53:40 -0700281 /* Set SPI (primary CBFS media) clock to 50MHz. */
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700282 /* if this is uncommented SPI will not work correctly. */
Gabe Blackd3163ab2013-05-16 05:53:40 -0700283 clock_set_rate(PERIPH_ID_SPI1, 50000000);
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700284 simple_spi_test();
Gabe Blackd3163ab2013-05-16 05:53:40 -0700285 entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700286 simple_spi_test();
Gabe Blackd3163ab2013-05-16 05:53:40 -0700287 stage_exit(entry);
288}