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Gabe Blackd3163ab2013-05-16 05:53:40 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Samsung Electronics
5 * Copyright 2013 Google Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <stddef.h>
22#include <stdlib.h>
23#include <console/console.h>
24
25#include <cpu/samsung/exynos5420/gpio.h>
Gabe Blackd3163ab2013-05-16 05:53:40 -070026#include <cpu/samsung/exynos5420/dmc.h>
Ronald G. Minniche6af9292013-06-03 13:03:50 -070027#include <cpu/samsung/exynos5420/setup.h>
Gabe Blackd3163ab2013-05-16 05:53:40 -070028#include <cpu/samsung/exynos5420/clk.h>
29
Ronald G. Minniche6af9292013-06-03 13:03:50 -070030const struct mem_timings mem_timings = {
Gabe Blackd3163ab2013-05-16 05:53:40 -070031 .mem_manuf = MEM_MANUF_SAMSUNG,
32 .mem_type = DDR_MODE_DDR3,
33 .frequency_mhz = 800,
Gabe Blackd3163ab2013-05-16 05:53:40 -070034 .direct_cmd_msr = {
Ronald G. Minniche6af9292013-06-03 13:03:50 -070035 0x00020018, 0x00030000, 0x00010002, 0x00000d70
Gabe Blackd3163ab2013-05-16 05:53:40 -070036 },
37 .timing_ref = 0x000000bb,
Ronald G. Minniche6af9292013-06-03 13:03:50 -070038 .timing_row = 0x6836650f,
Gabe Blackd3163ab2013-05-16 05:53:40 -070039 .timing_data = 0x3630580b,
Ronald G. Minniche6af9292013-06-03 13:03:50 -070040 .timing_power = 0x41000a26,
Gabe Blackd3163ab2013-05-16 05:53:40 -070041 .phy0_dqs = 0x08080808,
42 .phy1_dqs = 0x08080808,
43 .phy0_dq = 0x08080808,
44 .phy1_dq = 0x08080808,
45 .phy0_tFS = 0x8,
46 .phy1_tFS = 0x8,
47 .phy0_pulld_dqs = 0xf,
48 .phy1_pulld_dqs = 0xf,
49
50 .lpddr3_ctrl_phy_reset = 0x1,
51 .ctrl_start_point = 0x10,
52 .ctrl_inc = 0x10,
53 .ctrl_start = 0x1,
54 .ctrl_dll_on = 0x1,
55 .ctrl_ref = 0x8,
56
57 .ctrl_force = 0x1a,
58 .ctrl_rdlat = 0x0b,
59 .ctrl_bstlen = 0x08,
60
61 .fp_resync = 0x8,
62 .iv_size = 0x7,
63 .dfi_init_start = 1,
64 .aref_en = 1,
65
66 .rd_fetch = 0x3,
67
Ronald G. Minniche6af9292013-06-03 13:03:50 -070068 .zq_mode_dds = 0x6,
Gabe Blackd3163ab2013-05-16 05:53:40 -070069 .zq_mode_term = 0x1,
70 .zq_mode_noterm = 1,
71
72 /*
73 * Dynamic Clock: Always Running
74 * Memory Burst length: 8
75 * Number of chips: 1
76 * Memory Bus width: 32 bit
77 * Memory Type: DDR3
78 * Additional Latancy for PLL: 0 Cycle
79 */
80 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
81 DMC_MEMCONTROL_DPWRDN_DISABLE |
82 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
83 DMC_MEMCONTROL_TP_DISABLE |
Ronald G. Minniche6af9292013-06-03 13:03:50 -070084 DMC_MEMCONTROL_DSREF_DISABLE |
Gabe Blackd3163ab2013-05-16 05:53:40 -070085 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
86 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
87 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
Ronald G. Minniche6af9292013-06-03 13:03:50 -070088 DMC_MEMCONTROL_NUM_CHIP_2 |
Gabe Blackd3163ab2013-05-16 05:53:40 -070089 DMC_MEMCONTROL_BL_8 |
90 DMC_MEMCONTROL_PZQ_DISABLE |
91 DMC_MEMCONTROL_MRR_BYTE_7_0,
Ronald G. Minniche6af9292013-06-03 13:03:50 -070092 .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
Gabe Blackd3163ab2013-05-16 05:53:40 -070093 DMC_MEMCONFIGx_CHIP_COL_10 |
94 DMC_MEMCONFIGx_CHIP_ROW_15 |
95 DMC_MEMCONFIGx_CHIP_BANK_8,
Gabe Blackd3163ab2013-05-16 05:53:40 -070096 .prechconfig_tp_cnt = 0xff,
97 .dpwrdn_cyc = 0xff,
98 .dsref_cyc = 0xffff,
99 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
100 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
101 DMC_CONCONTROL_RD_FETCH_DISABLE |
102 DMC_CONCONTROL_EMPTY_DISABLE |
103 DMC_CONCONTROL_AREF_EN_DISABLE |
104 DMC_CONCONTROL_IO_PD_CON_DISABLE,
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700105 .dmc_channels = 1,
Gabe Blackd3163ab2013-05-16 05:53:40 -0700106 .chips_per_channel = 2,
Ronald G. Minniche6af9292013-06-03 13:03:50 -0700107 .chips_to_configure = 2,
Gabe Blackd3163ab2013-05-16 05:53:40 -0700108 .send_zq_init = 1,
Gabe Blackd3163ab2013-05-16 05:53:40 -0700109 .gate_leveling_enable = 1,
Gabe Blackd3163ab2013-05-16 05:53:40 -0700110};