Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 - 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <stdlib.h> |
| 19 | #include <string.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <console/console.h> |
| 23 | #include <soc/pci_devs.h> |
| 24 | #include <soc/ramstage.h> |
| 25 | |
| 26 | /** |
| 27 | * Read the base address registers for a given device. |
| 28 | * |
| 29 | * @param dev Pointer to the dev structure. |
| 30 | * @param howmany How many registers to read. |
| 31 | */ |
| 32 | static void pci_read_bases(struct device *dev, unsigned int howmany) |
| 33 | { |
| 34 | unsigned long index; |
| 35 | |
| 36 | for (index = PCI_BASE_ADDRESS_0; |
| 37 | (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { |
| 38 | struct resource *resource; |
| 39 | resource = pci_get_resource(dev, index); |
| 40 | /** |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 41 | * Workaround for Denverton-NS silicon (Rev A0/A1 for CSME/IE, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 42 | * Rev B0 for CSME only) |
| 43 | * CSME&IEs KT IO bar must be 16-byte aligned |
| 44 | */ |
| 45 | if ((resource->flags & IORESOURCE_IO) && |
| 46 | (resource->align != 4)) { |
| 47 | printk(BIOS_DEBUG, |
| 48 | "CSME&IEs KT IO bar must be 16-byte aligned!\n"); |
| 49 | resource->align = 4; |
| 50 | resource->gran = 4; |
| 51 | resource->size = 16; |
| 52 | } |
| 53 | index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; |
| 54 | } |
| 55 | |
| 56 | compact_resources(dev); |
| 57 | } |
| 58 | |
| 59 | static void pci_csme_ie_kt_read_resources(device_t dev) |
| 60 | { |
| 61 | /** |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 62 | * CSME/IE KT has 2 BARs to check: |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 63 | * 0x10 - KT IO BAR |
| 64 | * 0x14 - KT Memory BAR |
| 65 | * CSME/IE KT has no Expansion ROM BAR to check: |
| 66 | * 0x30 - KT Host XRBAR, READ ONLY |
| 67 | */ |
| 68 | pci_read_bases(dev, 2); |
| 69 | } |
| 70 | |
| 71 | static struct device_operations csme_ie_kt_ops = { |
| 72 | .read_resources = pci_csme_ie_kt_read_resources, |
| 73 | .set_resources = pci_dev_set_resources, |
| 74 | .enable_resources = pci_dev_enable_resources, |
| 75 | .scan_bus = 0, |
| 76 | .init = 0, |
| 77 | .ops_pci = &soc_pci_ops, |
| 78 | }; |
| 79 | |
| 80 | static const unsigned short pci_device_ids[] = { |
| 81 | ME_MEKT_DEVID, /* DVN CSME KT */ |
| 82 | IE_MEKT_DEVID, /* DVN IE KT */ |
| 83 | 0 |
| 84 | }; |
| 85 | |
| 86 | static const struct pci_driver csme_ie_kt __pci_driver = { |
| 87 | .ops = &csme_ie_kt_ops, |
| 88 | .vendor = PCI_VENDOR_ID_INTEL, |
| 89 | .devices = pci_device_ids, |
| 90 | }; |