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Edward O'Callaghan3042af62019-10-30 16:18:25 +11001chip soc/intel/cannonlake
2
3 register "SerialIoDevMode" = "{
4 [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
5 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
6 [PchSerialIoIndexI2C2] = PchSerialIoPci,
7 [PchSerialIoIndexI2C3] = PchSerialIoPci,
8 [PchSerialIoIndexI2C4] = PchSerialIoPci,
9 [PchSerialIoIndexI2C5] = PchSerialIoPci,
10 [PchSerialIoIndexSPI0] = PchSerialIoPci,
11 [PchSerialIoIndexSPI1] = PchSerialIoPci,
12 [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
13 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
14 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
15 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
16 }"
17
Jamie Chen1d534982020-01-15 10:44:38 +080018 # USB configuration
19 register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2
20 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
21 register "usb2_ports[2]" = "{
22 .enable = 1,
23 .ocpin = OC3,
24 .tx_bias = USB2_BIAS_0MV,
25 .tx_emp_enable = USB2_PRE_EMP_ON,
26 .pre_emp_bias = USB2_BIAS_28P15MV,
27 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
28 }" # Type-A Port 3
29 register "usb2_ports[3]" = "{
30 .enable = 1,
31 .ocpin = OC1,
32 .tx_bias = USB2_BIAS_0MV,
33 .tx_emp_enable = USB2_PRE_EMP_ON,
34 .pre_emp_bias = USB2_BIAS_28P15MV,
35 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
36 }" # Type-A Port 1
37 register "usb2_ports[4]" = "{
38 .enable = 1,
39 .ocpin = OC_SKIP,
40 .tx_bias = USB2_BIAS_0MV,
41 .tx_emp_enable = USB2_PRE_EMP_ON,
42 .pre_emp_bias = USB2_BIAS_28P15MV,
43 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
44 }" # Type-A Port 4
45 register "usb2_ports[5]" = "{
46 .enable = 1,
47 .ocpin = OC0,
48 .tx_bias = USB2_BIAS_0MV,
49 .tx_emp_enable = USB2_PRE_EMP_ON,
50 .pre_emp_bias = USB2_BIAS_28P15MV,
51 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
52 }" # Type-A port 0
Kangheui Won40a1f702019-12-19 13:24:29 -080053 register "usb2_ports[6]" = "USB2_PORT_EMPTY"
Jamie Chen1d534982020-01-15 10:44:38 +080054 register "usb2_ports[7]" = "USB2_PORT_EMPTY"
55 register "usb2_ports[8]" = "USB2_PORT_EMPTY"
56 register "usb2_ports[9]" = "{
57 .enable = 1,
58 .ocpin = OC_SKIP,
59 .tx_bias = USB2_BIAS_0MV,
60 .tx_emp_enable = USB2_PRE_EMP_ON,
61 .pre_emp_bias = USB2_BIAS_28P15MV,
62 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
63 }" # BT
64
65 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2
66 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3
67 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
68 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
69 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
70 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
Kangheui Won40a1f702019-12-19 13:24:29 -080071
Kangheui Wonbd3037b2019-12-18 12:22:43 -080072 # Enable eMMC HS400
73 register "ScsEmmcHs400Enabled" = "1"
74
75 # EMMC Tx CMD Delay
76 # Refer to EDS-Vol2-14.3.7.
77 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
78 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
79 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
80
81 # EMMC TX DATA Delay 1
82 # Refer to EDS-Vol2-14.3.8.
83 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
84 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
85 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
86
87 # EMMC TX DATA Delay 2
88 # Refer to EDS-Vol2-14.3.9.
89 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
90 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
91 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
92 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
93 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
94
95 # EMMC RX CMD/DATA Delay 1
96 # Refer to EDS-Vol2-14.3.10.
97 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
98 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
99 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
100 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
101 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
102
103 # EMMC RX CMD/DATA Delay 2
104 # Refer to EDS-Vol2-14.3.12.
105 # [17:16] stands for Rx Clock before Output Buffer,
106 # 00: Rx clock after output buffer,
107 # 01: Rx clock before output buffer,
108 # 10: Automatic selection based on working mode.
109 # 11: Reserved
110 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
111 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
112 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
113
114 # EMMC Rx Strobe Delay
115 # Refer to EDS-Vol2-14.3.11.
116 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
117 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
118 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
119
Edward O'Callaghan295fdbe2019-12-20 11:47:29 +1100120 # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
121 register "PchHdaAudioLinkSsp1" = "0"
122 register "PchHdaAudioLinkDmic0" = "0"
123
Edward O'Callaghan3042af62019-10-30 16:18:25 +1100124 # Intel Common SoC Config
125 #+-------------------+---------------------------+
126 #| Field | Value |
127 #+-------------------+---------------------------+
128 #| GSPI0 | cr50 TPM. Early init is |
129 #| | required to set up a BAR |
130 #| | for TPM communication |
131 #| | before memory is up |
132 #| I2C0 | RFU |
133 #| I2C2 | PS175 |
134 #| I2C3 | MST |
135 #| I2C4 | Audio |
136 #+-------------------+---------------------------+
137 register "common_soc_config" = "{
138 .gspi[0] = {
139 .speed_mhz = 1,
140 .early_init = 1,
141 },
142 .i2c[0] = {
143 .speed = I2C_SPEED_FAST,
144 .rise_time_ns = 0,
145 .fall_time_ns = 0,
146 },
Edward O'Callaghand4823662019-12-15 23:29:49 +1100147 .i2c[2] = {
Edward O'Callaghan3042af62019-10-30 16:18:25 +1100148 .speed = I2C_SPEED_FAST,
149 .rise_time_ns = 0,
150 .fall_time_ns = 0,
151 },
152 .i2c[3] = {
153 .speed = I2C_SPEED_FAST,
154 .rise_time_ns = 0,
155 .fall_time_ns = 0,
156 },
157 .i2c[4] = {
158 .speed = I2C_SPEED_FAST,
159 .rise_time_ns = 0,
160 .fall_time_ns = 0,
161 },
162 }"
163
Edward O'Callaghanb61f33c2019-12-18 11:04:20 +1100164 # PCIe port 7 for LAN
165 register "PcieRpEnable[6]" = "1"
166 register "PcieRpLtrEnable[6]" = "1"
167 # Uses CLK SRC 0
168 register "PcieClkSrcUsage[0]" = "6"
169 register "PcieClkSrcClkReq[0]" = "0"
170
Edward O'Callaghan3042af62019-10-30 16:18:25 +1100171 # GPIO for SD card detect
172 register "sdcard_cd_gpio" = "vSD3_CD_B"
173
Tim Chen6ce42612020-01-17 15:00:00 +0800174 # SATA port 1 Gen3 Strength
175 # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
176 register "sata_port[1].TxGen3DeEmphEnable" = "1"
177 register "sata_port[1].TxGen3DeEmph" = "0x20"
178
Edward O'Callaghan3042af62019-10-30 16:18:25 +1100179 device domain 0 on
Kangheui Won40a1f702019-12-19 13:24:29 -0800180 device pci 14.0 on
181 chip drivers/usb/acpi
182 device usb 0.0 on
183 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100184 register "desc" = ""USB2 Type-A Front Left""
Jamie Chen1d534982020-01-15 10:44:38 +0800185 register "type" = "UPC_TYPE_A"
186 device usb 2.0 on end
187 end
188 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100189 register "desc" = ""USB2 Type-C Port Rear""
Jamie Chen1d534982020-01-15 10:44:38 +0800190 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
191 device usb 2.1 on end
192 end
193 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100194 register "desc" = ""USB2 Type-A Front Right""
Jamie Chen1d534982020-01-15 10:44:38 +0800195 register "type" = "UPC_TYPE_A"
196 device usb 2.2 on end
197 end
198 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100199 register "desc" = ""USB2 Type-A Rear Right""
Jamie Chen1d534982020-01-15 10:44:38 +0800200 register "type" = "UPC_TYPE_A"
201 device usb 2.3 on end
202 end
203 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100204 register "desc" = ""USB2 Type-A Rear Middle""
Kangheui Won40a1f702019-12-19 13:24:29 -0800205 register "type" = "UPC_TYPE_A"
206 device usb 2.4 on end
207 end
208 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100209 register "desc" = ""USB2 Type-A Rear Left""
Kangheui Won40a1f702019-12-19 13:24:29 -0800210 register "type" = "UPC_TYPE_A"
211 device usb 2.5 on end
212 end
213 chip drivers/usb/acpi
214 device usb 2.6 off end
215 end
216 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100217 register "desc" = ""USB3 Type-A Front Left""
Jamie Chen1d534982020-01-15 10:44:38 +0800218 register "type" = "UPC_TYPE_USB3_A"
219 device usb 3.0 on end
220 end
221 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100222 register "desc" = ""USB3 Type-A Front Right""
Jamie Chen1d534982020-01-15 10:44:38 +0800223 register "type" = "UPC_TYPE_USB3_A"
224 device usb 3.1 on end
225 end
226 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100227 register "desc" = ""USB3 Type-A Rear Right""
Jamie Chen1d534982020-01-15 10:44:38 +0800228 register "type" = "UPC_TYPE_USB3_A"
229 device usb 3.2 on end
230 end
231 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100232 register "desc" = ""USB3 Type-C Rear""
Jamie Chen1d534982020-01-15 10:44:38 +0800233 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
234 device usb 3.3 on end
235 end
236 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100237 register "desc" = ""USB3 Type-A Rear Left""
Kangheui Won40a1f702019-12-19 13:24:29 -0800238 register "type" = "UPC_TYPE_USB3_A"
239 device usb 3.4 on end
240 end
241 chip drivers/usb/acpi
Edward O'Callaghan73692e82020-01-20 13:51:15 +1100242 register "desc" = ""USB3 Type-A Rear Middle""
Kangheui Won40a1f702019-12-19 13:24:29 -0800243 register "type" = "UPC_TYPE_USB3_A"
244 device usb 3.5 on end
245 end
246 end
247 end
248 end # USB xHCI
Edward O'Callaghan3042af62019-10-30 16:18:25 +1100249 device pci 15.0 off
250 # RFU - Reserved for Future Use.
251 end # I2C #0
252 device pci 15.1 off end # I2C #1
Edward O'Callaghand4823662019-12-15 23:29:49 +1100253 device pci 15.2 on end # I2C #2, PCON PS175.
Edward O'Callaghanec35a3d2020-01-02 16:12:58 +1100254 device pci 15.3 on end # I2C #3, Realtek RTD2142.
Edward O'Callaghan3042af62019-10-30 16:18:25 +1100255 device pci 19.0 on
256 chip drivers/i2c/generic
257 register "hid" = ""10EC5682""
258 register "name" = ""RT58""
259 register "desc" = ""Realtek RT5682""
260 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
261 register "property_count" = "1"
262 # Set the jd_src to RT5668_JD1 for jack detection
263 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
264 register "property_list[0].name" = ""realtek,jd-src""
265 register "property_list[0].integer" = "1"
266 device i2c 1a on end
267 end
268 end #I2C #4
Kangheui Wonbd3037b2019-12-18 12:22:43 -0800269 device pci 1a.0 on end # eMMC
Edward O'Callaghan731e6282019-12-30 19:27:53 +1100270 device pci 1c.0 on
271 chip drivers/net
272 register "customized_leds" = "0x05af"
273 device pci 00.0 on end
274 end
275 end # FSP requires func0 be enabled.
Edward O'Callaghane8b7ff12019-12-23 23:12:19 +1100276 device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1).
Edward O'Callaghan3042af62019-10-30 16:18:25 +1100277 device pci 1e.3 off end # GSPI #1
278 end
279
Jamie Chen951a6202020-01-20 18:06:19 +0800280 # VR Settings Configuration for 4 Domains
281 #+----------------+-------+-------+-------+-------+
282 #| Domain/Setting | SA | IA | GTUS | GTS |
283 #+----------------+-------+-------+-------+-------+
284 #| Psi1Threshold | 20A | 20A | 20A | 20A |
285 #| Psi2Threshold | 5A | 5A | 5A | 5A |
286 #| Psi3Threshold | 1A | 1A | 1A | 1A |
287 #| Psi3Enable | 1 | 1 | 1 | 1 |
288 #| Psi4Enable | 1 | 1 | 1 | 1 |
289 #| ImonSlope | 0 | 0 | 0 | 0 |
290 #| ImonOffset | 0 | 0 | 0 | 0 |
291 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
292 #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
293 #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
294 #+----------------+-------+-------+-------+-------+
295 #Note: IccMax settings are moved to SoC code
296 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
297 .vr_config_enable = 1,
298 .psi1threshold = VR_CFG_AMP(20),
299 .psi2threshold = VR_CFG_AMP(5),
300 .psi3threshold = VR_CFG_AMP(1),
301 .psi3enable = 1,
302 .psi4enable = 1,
303 .imon_slope = 0x0,
304 .imon_offset = 0x0,
305 .icc_max = 0,
306 .voltage_limit = 1520,
307 .ac_loadline = 1004,
308 .dc_loadline = 1004,
309 }"
310
311 register "domain_vr_config[VR_IA_CORE]" = "{
312 .vr_config_enable = 1,
313 .psi1threshold = VR_CFG_AMP(20),
314 .psi2threshold = VR_CFG_AMP(5),
315 .psi3threshold = VR_CFG_AMP(1),
316 .psi3enable = 1,
317 .psi4enable = 1,
318 .imon_slope = 0x0,
319 .imon_offset = 0x0,
320 .icc_max = 0,
321 .voltage_limit = 1520,
322 .ac_loadline = 181,
323 .dc_loadline = 181,
324 }"
325
326 register "domain_vr_config[VR_GT_UNSLICED]" = "{
327 .vr_config_enable = 1,
328 .psi1threshold = VR_CFG_AMP(20),
329 .psi2threshold = VR_CFG_AMP(5),
330 .psi3threshold = VR_CFG_AMP(1),
331 .psi3enable = 1,
332 .psi4enable = 1,
333 .imon_slope = 0x0,
334 .imon_offset = 0x0,
335 .icc_max = 0,
336 .voltage_limit = 1520,
337 .ac_loadline = 319,
338 .dc_loadline = 319,
339 }"
340
341 register "domain_vr_config[VR_GT_SLICED]" = "{
342 .vr_config_enable = 1,
343 .psi1threshold = VR_CFG_AMP(20),
344 .psi2threshold = VR_CFG_AMP(5),
345 .psi3threshold = VR_CFG_AMP(1),
346 .psi3enable = 1,
347 .psi4enable = 1,
348 .imon_slope = 0x0,
349 .imon_offset = 0x0,
350 .icc_max = 0,
351 .voltage_limit = 1520,
352 .ac_loadline = 319,
353 .dc_loadline = 319,
354 }"
355
Edward O'Callaghan3042af62019-10-30 16:18:25 +1100356end