blob: ae645a5e3e6437829e61b70683e23658aff104a2 [file] [log] [blame]
Shaunak Sahabd427802017-07-18 00:19:33 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#include <arch/acpigen.h>
17#include <arch/ioapic.h>
18#include <arch/smp/mpspec.h>
19#include <bootstate.h>
20#include <cbmem.h>
Aaron Durbin64031672018-04-21 14:45:32 -060021#include <compiler.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070022#include <cpu/intel/reset.h>
23#include <cpu/intel/turbo.h>
24#include <cpu/x86/msr.h>
25#include <cpu/x86/smm.h>
26#include <intelblocks/acpi.h>
27#include <intelblocks/msr.h>
28#include <intelblocks/pmclib.h>
Duncan Laurie93bbd412017-11-11 20:03:29 -080029#include <intelblocks/uart.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070030#include <soc/gpio.h>
31#include <soc/iomap.h>
32#include <soc/nvs.h>
33#include <soc/pm.h>
34
35unsigned long acpi_fill_mcfg(unsigned long current)
36{
37 /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
38 current += acpi_create_mcfg_mmconfig((void *)current,
39 CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
Duncan Lauriefd50b7c2018-03-02 14:47:11 -080040 (CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
Shaunak Sahabd427802017-07-18 00:19:33 -070041 return current;
42}
43
44static int acpi_sci_irq(void)
45{
46 int sci_irq = 9;
47 uint32_t scis;
48
49 scis = soc_read_sci_irq_select();
50 scis &= SCI_IRQ_SEL;
51 scis >>= SCI_IRQ_ADJUST;
52
53 /* Determine how SCI is routed. */
54 switch (scis) {
55 case SCIS_IRQ9:
56 case SCIS_IRQ10:
57 case SCIS_IRQ11:
58 sci_irq = scis - SCIS_IRQ9 + 9;
59 break;
60 case SCIS_IRQ20:
61 case SCIS_IRQ21:
62 case SCIS_IRQ22:
63 case SCIS_IRQ23:
64 sci_irq = scis - SCIS_IRQ20 + 20;
65 break;
66 default:
67 printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
68 sci_irq = 9;
69 break;
70 }
71
72 printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
73 return sci_irq;
74}
75
76static unsigned long acpi_madt_irq_overrides(unsigned long current)
77{
78 int sci = acpi_sci_irq();
79 uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
80
81 /* INT_SRC_OVR */
82 current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
83
84 flags |= soc_madt_sci_irq_polarity(sci);
85
86 /* SCI */
87 current +=
88 acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
89
90 return current;
91}
92
93unsigned long acpi_fill_madt(unsigned long current)
94{
95 /* Local APICs */
96 current = acpi_create_madt_lapics(current);
97
98 /* IOAPIC */
99 current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0);
100
101 return acpi_madt_irq_overrides(current);
102}
103
Aaron Durbin64031672018-04-21 14:45:32 -0600104__weak void soc_fill_fadt(acpi_fadt_t *fadt)
Shaunak Sahabd427802017-07-18 00:19:33 -0700105{
106}
107
108void acpi_fill_fadt(acpi_fadt_t *fadt)
109{
110 const uint16_t pmbase = ACPI_BASE_ADDRESS;
111
112 /* Use ACPI 3.0 revision. */
113 fadt->header.revision = ACPI_FADT_REV_ACPI_3_0;
114
115 fadt->sci_int = acpi_sci_irq();
116 fadt->smi_cmd = APM_CNT;
117 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
118 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
119 fadt->s4bios_req = 0x0;
120 fadt->pstate_cnt = 0;
121
122 fadt->pm1a_evt_blk = pmbase + PM1_STS;
123 fadt->pm1b_evt_blk = 0x0;
124 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
125 fadt->pm1b_cnt_blk = 0x0;
126
127 fadt->gpe0_blk = pmbase + GPE0_STS(0);
128
129 fadt->pm1_evt_len = 4;
130 fadt->pm1_cnt_len = 2;
131
132 /* GPE0 STS/EN pairs each 32 bits wide. */
133 fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
134
135 fadt->flush_size = 0x400; /* twice of cache size */
136 fadt->flush_stride = 0x10; /* Cache line width */
137 fadt->duty_offset = 1;
138 fadt->day_alrm = 0xd;
139
140 fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
141 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
142 ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
143 ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
144
145 fadt->reset_reg.space_id = 1;
146 fadt->reset_reg.bit_width = 8;
147 fadt->reset_reg.addrl = RST_CNT;
148 fadt->reset_value = RST_CPU | SYS_RST;
149
150 fadt->x_pm1a_evt_blk.space_id = 1;
151 fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
152 fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
153
154 fadt->x_pm1b_evt_blk.space_id = 1;
155
156 fadt->x_pm1a_cnt_blk.space_id = 1;
157 fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
158 fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
159
160 fadt->x_pm1b_cnt_blk.space_id = 1;
161
162 fadt->x_gpe1_blk.space_id = 1;
163
164 soc_fill_fadt(fadt);
165}
166
Elyes HAOUAS68c851b2018-06-12 22:06:09 +0200167unsigned long southbridge_write_acpi_tables(struct device *device,
Shaunak Sahabd427802017-07-18 00:19:33 -0700168 unsigned long current,
169 struct acpi_rsdp *rsdp)
170{
Duncan Laurie93bbd412017-11-11 20:03:29 -0800171 current = acpi_write_dbg2_pci_uart(rsdp, current,
Subrata Banikafa07f72018-05-24 12:21:06 +0530172 uart_get_device(),
Duncan Laurie93bbd412017-11-11 20:03:29 -0800173 ACPI_ACCESS_SIZE_DWORD_ACCESS);
Shaunak Sahabd427802017-07-18 00:19:33 -0700174 return acpi_write_hpet(device, current, rsdp);
175}
176
Aaron Durbin64031672018-04-21 14:45:32 -0600177__weak
Shaunak Sahabd427802017-07-18 00:19:33 -0700178uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
179 const struct chipset_power_state *ps)
180{
181 return generic_pm1_en;
182}
183
184/*
185 * Save wake source information for calculating ACPI _SWS values
186 *
187 * @pm1: PM1_STS register with only enabled events set
188 * @gpe0: GPE0_STS registers with only enabled events set
189 *
190 * return the number of registers in the gpe0 array or -1 if nothing
191 * is provided by this function.
192 */
193
194static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0)
195{
196 struct chipset_power_state *ps;
197 static uint32_t gpe0_sts[GPE0_REG_MAX];
198 uint32_t pm1_en;
199 int i;
200
201 ps = cbmem_find(CBMEM_ID_POWER_STATE);
202 if (ps == NULL)
203 return -1;
204
205 /*
206 * PM1_EN to check the basic wake events which can happen through
207 * powerbtn or any other wake source like lidopen, key board press etc.
208 */
209 pm1_en = ps->pm1_en;
210
211 pm1_en = acpi_fill_soc_wake(pm1_en, ps);
212
213 *pm1 = ps->pm1_sts & pm1_en;
214
215 /* Mask off GPE0 status bits that are not enabled */
216 *gpe0 = &gpe0_sts[0];
217 for (i = 0; i < GPE0_REG_MAX; i++)
218 gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
219
220 return GPE0_REG_MAX;
221}
222
Aaron Durbin64031672018-04-21 14:45:32 -0600223__weak void acpi_create_gnvs(struct global_nvs_t *gnvs)
Shaunak Sahabd427802017-07-18 00:19:33 -0700224{
225}
226
Elyes HAOUAS68c851b2018-06-12 22:06:09 +0200227void southbridge_inject_dsdt(struct device *device)
Shaunak Sahabd427802017-07-18 00:19:33 -0700228{
229 struct global_nvs_t *gnvs;
230
231 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
232 if (!gnvs) {
233 gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
234 if (gnvs)
235 memset(gnvs, 0, sizeof(*gnvs));
236 }
237
238 if (gnvs) {
239 acpi_create_gnvs(gnvs);
Shaunak Sahabd427802017-07-18 00:19:33 -0700240 /* And tell SMI about it */
241 smm_setup_structures(gnvs, NULL, NULL);
242
243 /* Add it to DSDT. */
244 acpigen_write_scope("\\");
245 acpigen_write_name_dword("NVSA", (uintptr_t) gnvs);
246 acpigen_pop_len();
247 }
248}
249
250static int calculate_power(int tdp, int p1_ratio, int ratio)
251{
252 u32 m;
253 u32 power;
254
255 /*
256 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
257 *
258 * Power = (ratio / p1_ratio) * m * tdp
259 */
260
261 m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
262 m = (m * m) / 1000;
263
264 power = ((ratio * 100000 / p1_ratio) / 100);
265 power *= (m / 100) * (tdp / 1000);
266 power /= 1000;
267
268 return power;
269}
270
271static int get_cores_per_package(void)
272{
273 struct cpuinfo_x86 c;
274 struct cpuid_result result;
275 int cores = 1;
276
277 get_fms(&c, cpuid_eax(1));
278 if (c.x86 != 6)
279 return 1;
280
281 result = cpuid_ext(0xb, 1);
282 cores = result.ebx & 0xff;
283
284 return cores;
285}
286
287static void generate_c_state_entries(void)
288{
289 acpi_cstate_t *c_state_map;
290 size_t entries;
291
292 c_state_map = soc_get_cstate_map(&entries);
293
294 /* Generate C-state tables */
295 acpigen_write_CST_package(c_state_map, entries);
296}
297
298void generate_p_state_entries(int core, int cores_per_package)
299{
300 int ratio_min, ratio_max, ratio_turbo, ratio_step;
301 int coord_type, power_max, num_entries;
302 int ratio, power, clock, clock_max;
303
304 coord_type = cpu_get_coord_type();
305 ratio_min = cpu_get_min_ratio();
306 ratio_max = cpu_get_max_ratio();
307 clock_max = (ratio_max * cpu_get_bus_clock()) / KHz;
308
309 /* Calculate CPU TDP in mW */
310 power_max = cpu_get_power_max();
311
312 /* Write _PCT indicating use of FFixedHW */
313 acpigen_write_empty_PCT();
314
315 /* Write _PPC with no limit on supported P-state */
316 acpigen_write_PPC_NVS();
317 /* Write PSD indicating configured coordination type */
318 acpigen_write_PSD_package(core, 1, coord_type);
319
320 /* Add P-state entries in _PSS table */
321 acpigen_write_name("_PSS");
322
323 /* Determine ratio points */
324 ratio_step = PSS_RATIO_STEP;
325 num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
326 if (num_entries > PSS_MAX_ENTRIES) {
327 ratio_step += 1;
328 num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
329 }
330
331 /* P[T] is Turbo state if enabled */
332 if (get_turbo_state() == TURBO_ENABLED) {
333 /* _PSS package count including Turbo */
334 acpigen_write_package(num_entries + 2);
335 ratio_turbo = cpu_get_max_turbo_ratio();
336
337 /* Add entry for Turbo ratio */
338 acpigen_write_PSS_package(clock_max + 1, /* MHz */
339 power_max, /* mW */
340 PSS_LATENCY_TRANSITION,/* lat1 */
341 PSS_LATENCY_BUSMASTER,/* lat2 */
342 ratio_turbo << 8, /* control */
343 ratio_turbo << 8); /* status */
344 } else {
345 /* _PSS package count without Turbo */
346 acpigen_write_package(num_entries + 1);
347 }
348
349 /* First regular entry is max non-turbo ratio */
350 acpigen_write_PSS_package(clock_max, /* MHz */
351 power_max, /* mW */
352 PSS_LATENCY_TRANSITION,/* lat1 */
353 PSS_LATENCY_BUSMASTER,/* lat2 */
354 ratio_max << 8, /* control */
355 ratio_max << 8); /* status */
356
357 /* Generate the remaining entries */
358 for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
359 ratio >= ratio_min; ratio -= ratio_step) {
360
361 /* Calculate power at this ratio */
362 power = calculate_power(power_max, ratio_max, ratio);
363 clock = (ratio * cpu_get_bus_clock()) / KHz;
364
365 acpigen_write_PSS_package(clock, /* MHz */
366 power, /* mW */
367 PSS_LATENCY_TRANSITION,/* lat1 */
368 PSS_LATENCY_BUSMASTER,/* lat2 */
369 ratio << 8, /* control */
370 ratio << 8); /* status */
371 }
372 /* Fix package length */
373 acpigen_pop_len();
374}
375
376static acpi_tstate_t *soc_get_tss_table(int *entries)
377{
378 *entries = 0;
379 return NULL;
380}
381
382void generate_t_state_entries(int core, int cores_per_package)
383{
384 acpi_tstate_t *soc_tss_table;
385 int entries;
386
387 soc_tss_table = soc_get_tss_table(&entries);
388 if (entries == 0)
389 return;
390
391 /* Indicate SW_ALL coordination for T-states */
392 acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
393
394 /* Indicate FixedHW so OS will use MSR */
395 acpigen_write_empty_PTC();
396
397 /* Set NVS controlled T-state limit */
398 acpigen_write_TPC("\\TLVL");
399
400 /* Write TSS table for MSR access */
401 acpigen_write_TSS_package(entries, soc_tss_table);
402}
403
Aaron Durbin64031672018-04-21 14:45:32 -0600404__weak void soc_power_states_generation(int core_id,
Shaunak Sahabd427802017-07-18 00:19:33 -0700405 int cores_per_package)
406{
407}
408
Elyes HAOUAS68c851b2018-06-12 22:06:09 +0200409void generate_cpu_entries(struct device *device)
Shaunak Sahabd427802017-07-18 00:19:33 -0700410{
411 int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS;
412 int plen = 6;
413 int totalcores = dev_count_cpu();
414 int cores_per_package = get_cores_per_package();
415 int numcpus = totalcores / cores_per_package;
416
417 printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
418 numcpus, cores_per_package);
419
420 for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
421 for (core_id = 0; core_id < cores_per_package; core_id++) {
422 if (core_id > 0) {
423 pcontrol_blk = 0;
424 plen = 0;
425 }
426
427 /* Generate processor \_PR.CPUx */
428 acpigen_write_processor((cpu_id) * cores_per_package +
429 core_id, pcontrol_blk, plen);
430
431 /* Generate C-state tables */
432 generate_c_state_entries();
433
434 /* Soc specific power states generation */
435 soc_power_states_generation(core_id, cores_per_package);
436
437 acpigen_pop_len();
438 }
439 }
440}
441
442#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
443/* Save wake source data for ACPI _SWS methods in NVS */
444static void acpi_save_wake_source(void *unused)
445{
446 global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
447 uint32_t pm1, *gpe0;
448 int gpe_reg, gpe_reg_count;
449 int reg_size = sizeof(uint32_t) * 8;
450
451 if (!gnvs)
452 return;
453
454 gnvs->pm1i = -1;
455 gnvs->gpei = -1;
456
457 gpe_reg_count = acpi_fill_wake(&pm1, &gpe0);
458 if (gpe_reg_count < 0)
459 return;
460
461 /* Scan for first set bit in PM1 */
462 for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) {
463 if (pm1 & 1)
464 break;
465 pm1 >>= 1;
466 }
467
468 /* If unable to determine then return -1 */
469 if (gnvs->pm1i >= 16)
470 gnvs->pm1i = -1;
471
472 /* Scan for first set bit in GPE registers */
473 for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) {
474 uint32_t gpe = gpe0[gpe_reg];
475 int start = gpe_reg * reg_size;
476 int end = start + reg_size;
477
478 if (gpe == 0) {
479 if (!gnvs->gpei)
480 gnvs->gpei = end;
481 continue;
482 }
483
484 for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
485 if (gpe & 1)
486 break;
487 gpe >>= 1;
488 }
489 }
490
491 /* If unable to determine then return -1 */
492 if (gnvs->gpei >= gpe_reg_count * reg_size)
493 gnvs->gpei = -1;
494
495 printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
496 (long long)gnvs->pm1i, (long long)gnvs->gpei);
497}
498
499BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL);
500
501#endif