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Marc Jones24484842017-05-04 21:17:45 -06001/*
2 * This file is part of the coreboot project.
3 *
Marc Jones257db582017-06-18 17:33:30 -06004 * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc.
5 * Copyright (C) 2014 Google Inc.
Marc Jones24484842017-05-04 21:17:45 -06006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17/*
18 * ACPI - create the Fixed ACPI Description Tables (FADT)
19 */
20
21#include <string.h>
22#include <console/console.h>
23#include <arch/acpi.h>
Marc Jones257db582017-06-18 17:33:30 -060024#include <arch/acpigen.h>
Marc Jones24484842017-05-04 21:17:45 -060025#include <arch/io.h>
Marc Jones5ebc8652017-06-19 23:34:04 -060026#include <arch/ioapic.h>
Marshall Dawsone9b862e2017-09-22 15:14:46 -060027#include <cpu/x86/smm.h>
Marc Jones257db582017-06-18 17:33:30 -060028#include <cbmem.h>
Marc Jones24484842017-05-04 21:17:45 -060029#include <device/device.h>
Marc Jones6bfcf662017-08-06 17:42:35 -060030#include <device/pci.h>
Marc Jones257db582017-06-18 17:33:30 -060031#include <soc/acpi.h>
Chris Ching6a35fab2017-10-19 11:45:30 -060032#include <soc/pci_devs.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -060033#include <soc/southbridge.h>
Marc Jones257db582017-06-18 17:33:30 -060034#include <soc/nvs.h>
Richard Spiegel93459d62018-05-16 14:08:33 -070035#include <soc/gpio.h>
Marc Jones24484842017-05-04 21:17:45 -060036
Marc Jones5ebc8652017-06-19 23:34:04 -060037unsigned long acpi_fill_madt(unsigned long current)
38{
39 /* create all subtables for processors */
40 current = acpi_create_madt_lapics(current);
41
42 /* Write Kern IOAPIC, only one */
43 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
44 CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
45
46 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
47 CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24);
48
49 /* 0: mean bus 0--->ISA */
50 /* 0: PIC 0 */
51 /* 2: APIC 2 */
52 /* 5 mean: 0101 --> Edge-triggered, Active high */
53 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
54 current, 0, 0, 2, 0);
55 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
56 current, 0, 9, 9, 0xF);
57
58 /* create all subtables for processors */
59 current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
60 0xff, 5, 1);
61 /* 1: LINT1 connect to NMI */
62
63 return current;
64}
65
Marc Jones24484842017-05-04 21:17:45 -060066/*
67 * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
68 * in the ACPI 3.0b specification.
69 */
Marshall Dawson4e101ad2017-06-15 12:17:38 -060070void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
Marc Jones24484842017-05-04 21:17:45 -060071{
72 acpi_header_t *header = &(fadt->header);
73
74 printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE);
75
76 /* Prepare the header */
77 memset((void *)fadt, 0, sizeof(acpi_fadt_t));
78 memcpy(header->signature, "FACP", 4);
79 header->length = sizeof(acpi_fadt_t);
80 header->revision = ACPI_FADT_REV_ACPI_3_0;
81 memcpy(header->oem_id, OEM_ID, 6);
82 memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
83 memcpy(header->asl_compiler_id, ASLC, 4);
84 header->asl_compiler_revision = 0;
85
86 fadt->firmware_ctrl = (u32) facs;
87 fadt->dsdt = (u32) dsdt;
88 fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */
89 fadt->preferred_pm_profile = FADT_PM_PROFILE;
Marc Jonesdfeb1c42017-08-07 19:08:24 -060090 fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */
Marc Jones24484842017-05-04 21:17:45 -060091
92 if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
Marshall Dawsone9b862e2017-09-22 15:14:46 -060093 fadt->smi_cmd = APM_CNT;
94 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
95 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
Marc Jones24484842017-05-04 21:17:45 -060096 fadt->s4bios_req = 0; /* Not supported */
97 fadt->pstate_cnt = 0; /* Not supported */
98 fadt->cst_cnt = 0; /* Not supported */
99 outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */
100 } else {
101 fadt->smi_cmd = 0; /* disable system management mode */
102 fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */
103 fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */
104 fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */
105 fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */
106 fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */
107 outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
108 }
109
110 fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
111 fadt->pm1b_evt_blk = 0x0000;
112 fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
113 fadt->pm1b_cnt_blk = 0x0000;
114 fadt->pm2_cnt_blk = 0x0000;
115 fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
116 fadt->gpe0_blk = ACPI_GPE0_BLK;
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600117 fadt->gpe1_blk = 0x0000; /* No gpe1 block */
Marc Jones24484842017-05-04 21:17:45 -0600118
119 fadt->pm1_evt_len = 4; /* 32 bits */
120 fadt->pm1_cnt_len = 2; /* 16 bits */
121 fadt->pm2_cnt_len = 0;
122 fadt->pm_tmr_len = 4; /* 32 bits */
123 fadt->gpe0_blk_len = 8; /* 64 bits */
124 fadt->gpe1_blk_len = 0;
125 fadt->gpe1_base = 0;
126
127 fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
128 fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
129 fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
130 fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
131 fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
132 fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
133 fadt->day_alrm = 0; /* 0x7d these have to be */
134 fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
135 fadt->century = 0; /* 0x7f to make rtc alarm work */
136 fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */
137 fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */
138 fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
139 ACPI_FADT_C1_SUPPORTED |
140 ACPI_FADT_SLEEP_BUTTON |
141 ACPI_FADT_S4_RTC_WAKE |
142 ACPI_FADT_32BIT_TIMER |
143 ACPI_FADT_RESET_REGISTER |
144 ACPI_FADT_PCI_EXPRESS_WAKE |
145 ACPI_FADT_PLATFORM_CLOCK |
146 ACPI_FADT_S4_RTC_VALID |
147 ACPI_FADT_REMOTE_POWER_ON;
148
149 /* Format is from 5.2.3.1: Generic Address Structure */
150 /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
151 /* 8 bit write of value 0x06 to 0xCF9 in IO space */
152 fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
153 fadt->reset_reg.bit_width = 8;
154 fadt->reset_reg.bit_offset = 0;
155 fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
Marshall Dawson4e101ad2017-06-15 12:17:38 -0600156 fadt->reset_reg.addrl = SYS_RESET;
Marc Jones24484842017-05-04 21:17:45 -0600157 fadt->reset_reg.addrh = 0x0;
158
159 fadt->reset_value = 6;
160
161 fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */
162 fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */
163 fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */
164
165 fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */
166 fadt->x_firmware_ctl_h = 0;
167 fadt->x_dsdt_l = (u32) dsdt;
168 fadt->x_dsdt_h = 0;
169
170 fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
171 fadt->x_pm1a_evt_blk.bit_width = 32;
172 fadt->x_pm1a_evt_blk.bit_offset = 0;
173 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
174 fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
175 fadt->x_pm1a_evt_blk.addrh = 0x0;
176
177 fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
178 fadt->x_pm1b_evt_blk.bit_width = 0;
179 fadt->x_pm1b_evt_blk.bit_offset = 0;
180 fadt->x_pm1b_evt_blk.access_size = 0;
181 fadt->x_pm1b_evt_blk.addrl = 0x0;
182 fadt->x_pm1b_evt_blk.addrh = 0x0;
183
184
185 fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
186 fadt->x_pm1a_cnt_blk.bit_width = 16;
187 fadt->x_pm1a_cnt_blk.bit_offset = 0;
188 fadt->x_pm1a_cnt_blk.access_size = 0;
189 fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
190 fadt->x_pm1a_cnt_blk.addrh = 0x0;
191
192 fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
193 fadt->x_pm1b_cnt_blk.bit_width = 0;
194 fadt->x_pm1b_cnt_blk.bit_offset = 0;
195 fadt->x_pm1b_cnt_blk.access_size = 0;
196 fadt->x_pm1b_cnt_blk.addrl = 0x0;
197 fadt->x_pm1b_cnt_blk.addrh = 0x0;
198
199 /*
Marshall Dawson4e101ad2017-06-15 12:17:38 -0600200 * Note: Under this current AMD C state implementation, this is no
201 * longer used and should not be reported to OS.
Marc Jones24484842017-05-04 21:17:45 -0600202 */
203 fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
204 fadt->x_pm2_cnt_blk.bit_width = 0;
205 fadt->x_pm2_cnt_blk.bit_offset = 0;
206 fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
207 fadt->x_pm2_cnt_blk.addrl = 0;
208 fadt->x_pm2_cnt_blk.addrh = 0x0;
209
210
211 fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
212 fadt->x_pm_tmr_blk.bit_width = 32;
213 fadt->x_pm_tmr_blk.bit_offset = 0;
214 fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
215 fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
216 fadt->x_pm_tmr_blk.addrh = 0x0;
217
218
219 fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
220 fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
221 fadt->x_gpe0_blk.bit_offset = 0;
222 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
223 fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
224 fadt->x_gpe0_blk.addrh = 0x0;
225
226
227 fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
228 fadt->x_gpe1_blk.bit_width = 0;
229 fadt->x_gpe1_blk.bit_offset = 0;
230 fadt->x_gpe1_blk.access_size = 0;
231 fadt->x_gpe1_blk.addrl = 0;
232 fadt->x_gpe1_blk.addrh = 0x0;
233
234 header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
235}
Marc Jones257db582017-06-18 17:33:30 -0600236
Elyes HAOUAS777ccd42018-05-22 10:52:05 +0200237void generate_cpu_entries(struct device *device)
Marc Jones6bfcf662017-08-06 17:42:35 -0600238{
Richard Spiegel3f16a0f2018-08-06 11:06:08 -0700239 int cores, cpu;
Elyes HAOUAS777ccd42018-05-22 10:52:05 +0200240 struct device *cdb_dev;
Marc Jones6bfcf662017-08-06 17:42:35 -0600241
242 /* Stoney Ridge is single node, just report # of cores */
Chris Ching6a35fab2017-10-19 11:45:30 -0600243 cdb_dev = dev_find_slot(0, NB_DEVFN);
Marc Jones6bfcf662017-08-06 17:42:35 -0600244 cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;
245
246 printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
247
Marc Jonese013df92017-08-23 16:28:02 -0600248 /* Generate BSP \_PR.P000 */
Richard Spiegel3f16a0f2018-08-06 11:06:08 -0700249 acpigen_write_processor(0, ACPI_GPE0_BLK, 6);
Marc Jones6bfcf662017-08-06 17:42:35 -0600250 acpigen_pop_len();
251
Marc Jonese013df92017-08-23 16:28:02 -0600252 /* Generate AP \_PR.Pxxx */
Marc Jones6bfcf662017-08-06 17:42:35 -0600253 for (cpu = 1; cpu < cores; cpu++) {
Richard Spiegel3f16a0f2018-08-06 11:06:08 -0700254 acpigen_write_processor(cpu, 0, 0);
Marc Jones6bfcf662017-08-06 17:42:35 -0600255 acpigen_pop_len();
256 }
257}
258
Elyes HAOUAS777ccd42018-05-22 10:52:05 +0200259unsigned long southbridge_write_acpi_tables(struct device *device,
Marc Jones257db582017-06-18 17:33:30 -0600260 unsigned long current,
261 struct acpi_rsdp *rsdp)
262{
263 return acpi_write_hpet(device, current, rsdp);
264}
265
266static void acpi_create_gnvs(struct global_nvs_t *gnvs)
267{
268 /* Clear out GNVS. */
269 memset(gnvs, 0, sizeof(*gnvs));
270
271 if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
272 gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
273
274 if (IS_ENABLED(CONFIG_CHROMEOS)) {
275 /* Initialize Verified Boot data */
276 chromeos_init_vboot(&gnvs->chromeos);
277 gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
278 }
279
280 /* Set unknown wake source */
281 gnvs->pm1i = ~0ULL;
Richard Spiegeldbee8ae2018-05-09 17:34:04 -0700282 gnvs->gpei = ~0ULL;
Marc Jones257db582017-06-18 17:33:30 -0600283
284 /* CPU core count */
285 gnvs->pcnt = dev_count_cpu();
286}
287
Elyes HAOUAS777ccd42018-05-22 10:52:05 +0200288void southbridge_inject_dsdt(struct device *device)
Marc Jones257db582017-06-18 17:33:30 -0600289{
290 struct global_nvs_t *gnvs;
291
292 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
293
294 if (gnvs) {
295 acpi_create_gnvs(gnvs);
Marc Jones257db582017-06-18 17:33:30 -0600296
297 /* Add it to DSDT */
298 acpigen_write_scope("\\");
299 acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
300 acpigen_pop_len();
301 }
302}
Richard Spiegel93459d62018-05-16 14:08:33 -0700303
304static void acpigen_soc_get_gpio_in_local5(uintptr_t addr)
305{
306 /*
307 * Store (\_SB.GPR2 (addr), Local5)
308 * \_SB.GPR2 is used to read control byte 2 from control register.
309 * / It is defined in gpio_lib.asl.
310 */
311 acpigen_write_store();
312 acpigen_emit_namestring("\\_SB.GPR2");
313 acpigen_write_integer(addr);
314 acpigen_emit_byte(LOCAL5_OP);
315}
316
317static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
318{
319 if (gpio_num >= GPIO_TOTAL_PINS) {
320 printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
321 " %d\n", gpio_num, GPIO_TOTAL_PINS);
322 return -1;
323 }
324 uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
325
326 acpigen_soc_get_gpio_in_local5(addr);
327
328 /* If (And (Local5, mask)) */
329 acpigen_write_if_and(LOCAL5_OP, mask);
330
331 /* Store (One, Local0) */
332 acpigen_write_store_ops(ONE_OP, LOCAL0_OP);
333
334 acpigen_pop_len(); /* If */
335
336 /* Else */
337 acpigen_write_else();
338
339 /* Store (Zero, Local0) */
340 acpigen_write_store_ops(ZERO_OP, LOCAL0_OP);
341
342 acpigen_pop_len(); /* Else */
343
344 return 0;
345}
346
347static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
348{
349 if (gpio_num >= GPIO_TOTAL_PINS) {
350 printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
351 " %d\n", gpio_num, GPIO_TOTAL_PINS);
352 return -1;
353 }
354 uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
355
Kevin Chiud837e662018-07-03 19:13:34 +0800356 /* Store (0x40, Local0) */
357 acpigen_write_store();
358 acpigen_write_integer(GPIO_PIN_OUT);
359 acpigen_emit_byte(LOCAL0_OP);
360
Richard Spiegel93459d62018-05-16 14:08:33 -0700361 acpigen_soc_get_gpio_in_local5(addr);
362
363 if (val) {
364 /* Or (Local5, GPIO_PIN_OUT, Local5) */
Kevin Chiud837e662018-07-03 19:13:34 +0800365 acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP);
Richard Spiegel93459d62018-05-16 14:08:33 -0700366 } else {
367 /* Not (GPIO_PIN_OUT, Local6) */
Kevin Chiud837e662018-07-03 19:13:34 +0800368 acpigen_write_not(LOCAL0_OP, LOCAL6_OP);
Richard Spiegel93459d62018-05-16 14:08:33 -0700369
370 /* And (Local5, Local6, Local5) */
371 acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP);
372 }
373
374 /*
375 * SB.GPW2 (addr, Local5)
376 * \_SB.GPW2 is used to write control byte in control register
377 * / byte 2. It is defined in gpio_lib.asl.
378 */
379 acpigen_emit_namestring("\\_SB.GPW2");
380 acpigen_write_integer(addr);
381 acpigen_emit_byte(LOCAL5_OP);
382
383 return 0;
384}
385
386int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
387{
388 return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN);
389}
390
391int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
392{
393 return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT);
394}
395
396int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
397{
398 return acpigen_soc_set_gpio_val(gpio_num, 1);
399}
400
401int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
402{
403 return acpigen_soc_set_gpio_val(gpio_num, 0);
404}