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Alexandru Gagniuce644bad2012-08-07 19:38:32 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Alexandru Gagniuce644bad2012-08-07 19:38:32 -050015 */
16
17#include "update_ucode.h"
18#include <console/console.h>
19#include <device/device.h>
20#include <cpu/cpu.h>
21#include <cpu/x86/mtrr.h>
22#include <cpu/x86/msr.h>
23#include <cpu/x86/lapic.h>
24#include <cpu/x86/cache.h>
25#include <delay.h>
26
27#define MODEL_NANO 0x2
28#define MODEL_NANO_3000_B0 0x8
29#define MODEL_NANO_3000_B2 0xa
30
31#define MSR_IA32_PERF_STATUS 0x00000198
32#define MSR_IA32_PERF_CTL 0x00000199
33#define MSR_IA32_MISC_ENABLE 0x000001a0
34#define NANO_MYSTERIOUS_MSR 0x120e
35
36static void nano_finish_fid_vid_transition(void)
37{
38
39 msr_t msr;
40 /* Wait until the power transition ends */
41 int cnt = 0;
42 do {
43 udelay(16);
44 msr = rdmsr(MSR_IA32_PERF_STATUS);
45 cnt++;
46 if (cnt > 128) {
47 printk(BIOS_WARNING,
48 "Error while updating multiplier and voltage\n");
49 break;
50 }
51 } while (msr.lo & ((1 << 16) | (1 << 17)));
52
53 /* Print the new FID and Voltage */
54 u8 cur_vid = (msr.lo >> 0) & 0xff;
55 u8 cur_fid = (msr.lo >> 8) & 0xff;
56 printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid);
57 printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid);
58}
59
60static void nano_set_max_fid_vid(void)
61{
62 msr_t msr;
63 /* Get voltage and frequency info */
64 msr = rdmsr(MSR_IA32_PERF_STATUS);
65 u8 min_fid = (msr.hi >> 24);
66 u8 max_fid = (msr.hi >> 8) & 0xff;
67 u8 min_vid = (msr.hi >> 16) & 0xff;
68 u8 max_vid = (msr.hi >> 0) & 0xff;
69 u8 cur_vid = (msr.lo >> 0) & 0xff;
70 u8 cur_fid = (msr.lo >> 8) & 0xff;
71
72 printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
73 cur_fid, min_fid, max_fid);
74 printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n",
75 cur_vid, min_vid, max_vid);
76
Elyes HAOUAScbe7464c2016-08-23 21:07:28 +020077 if ( (cur_fid != max_fid) || (cur_vid != max_vid) ) {
Alexandru Gagniuce644bad2012-08-07 19:38:32 -050078 /* Set highest frequency and VID */
79 msr.lo = msr.hi;
80 msr.hi = 0;
81 wrmsr(MSR_IA32_PERF_CTL, msr);
82 /* Wait for the transition to complete, otherwise, the CPU
83 * might reset itself repeatedly */
84 nano_finish_fid_vid_transition();
85 }
86 /* As a side note, if we didn't update the microcode by this point, the
87 * second PLL will not lock correctly. The clock will still be provided
88 * by the first PLL, and execution will continue normally, ___until___
89 * the CPU switches PLL. Once that happens we will no longer have a
90 * working clock source, and the CPU will hang
91 * Moral of the story: update the microcode, or don't change FID
92 * This check is handled before calling nano_power() */
93}
94
95static void nano_power(void)
96{
97 msr_t msr;
98 /* Enable Powersaver */
99 msr = rdmsr(MSR_IA32_MISC_ENABLE);
100 msr.lo |= (1 << 16);
101 wrmsr(MSR_IA32_MISC_ENABLE, msr);
102
103 /* Enable 6 bit or 7-bit VRM support
104 * This MSR is not documented by VIA docs, other than setting these
105 * bits */
106 msr = rdmsr(NANO_MYSTERIOUS_MSR);
Elyes HAOUAS168ef392017-06-27 22:54:42 +0200107 msr.lo |= ( (1 << 7) | (1 << 4) );
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500108 /* FIXME: Do we have a 6-bit or 7-bit VRM?
109 * set bit [5] for 7-bit, or don't set it for 6 bit VRM
110 * This will probably require a Kconfig option
111 * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */
Elyes HAOUAS168ef392017-06-27 22:54:42 +0200112 msr.lo |= (1 << 5);
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500113 wrmsr(NANO_MYSTERIOUS_MSR, msr);
114
115 /* Set the maximum frequency and voltage */
116 nano_set_max_fid_vid();
117
118 /* Enable TM3 */
119 msr = rdmsr(MSR_IA32_MISC_ENABLE);
Elyes HAOUAS168ef392017-06-27 22:54:42 +0200120 msr.lo |= ( (1 << 3) | (1 << 13) );
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500121 wrmsr(MSR_IA32_MISC_ENABLE, msr);
122
123 u8 stepping = ( cpuid_eax(0x1) ) &0xf;
Elyes HAOUAScbe7464c2016-08-23 21:07:28 +0200124 if (stepping >= MODEL_NANO_3000_B0) {
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500125 /* Hello Nano 3000. The Terminator needs a CPU upgrade */
126 /* Enable C1e, C2e, C3e, and C4e states */
127 msr = rdmsr(MSR_IA32_MISC_ENABLE);
Elyes HAOUAS168ef392017-06-27 22:54:42 +0200128 msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
129 msr.hi |= (1 << 0); /* C4e */
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500130 wrmsr(MSR_IA32_MISC_ENABLE, msr);
131 }
132
133 /* Lock on Powersaver */
134 msr = rdmsr(MSR_IA32_MISC_ENABLE);
Elyes HAOUAS168ef392017-06-27 22:54:42 +0200135 msr.lo |= (1 << 20);
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500136 wrmsr(MSR_IA32_MISC_ENABLE, msr);
137}
138
Edward O'Callaghan2c9d2cf2014-10-27 23:29:29 +1100139static void nano_init(struct device *dev)
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500140{
141 struct cpuinfo_x86 c;
142
143 get_fms(&c, dev->device);
144
145 /* We didn't test this on the Nano 1000/2000 series, so warn the user */
Elyes HAOUAScbe7464c2016-08-23 21:07:28 +0200146 if (c.x86_mask < MODEL_NANO_3000_B0) {
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500147 printk(BIOS_EMERG, "WARNING: This CPU has not been tested. "
Elyes HAOUAS7c8d74c2016-08-23 21:41:43 +0200148 "Please report any issues encountered.\n");
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500149 }
150 switch (c.x86_mask) {
151 case MODEL_NANO:
152 printk(BIOS_INFO, "VIA Nano");
153 break;
154 case MODEL_NANO_3000_B0:
155 printk(BIOS_INFO, "VIA Nano 3000 rev B0");
156 break;
157 case MODEL_NANO_3000_B2:
158 printk(BIOS_INFO, "VIA Nano 3000 rev B2");
159 break;
160 default:
161 printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask);
162 }
163 printk(BIOS_INFO, "\n");
164
165 /* We only read microcode from CBFS. If we don't have any microcode in
166 * CBFS, we'll just get back with 0 updates. User choice FTW. */
167 unsigned int n_updates = nano_update_ucode();
168
Elyes HAOUAScbe7464c2016-08-23 21:07:28 +0200169 if (n_updates != 0){
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500170 nano_power();
171 } else {
172 /* Changing the frequency or voltage without first updating the
173 * microcode will hang the CPU, so just don't do it */
174 printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n"
175 " Will not change frequency, as this may hang the CPU.\n");
176 }
177
178 /* Turn on cache */
179 x86_enable_cache();
180 /* Set up Memory Type Range Registers */
181 x86_setup_mtrrs();
182 x86_mtrr_check();
Elyes HAOUASd6e96862016-08-21 10:12:15 +0200183 /* Enable the local CPU APICs */
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500184 setup_lapic();
185}
186
187static struct device_operations cpu_dev_ops = {
188 .init = nano_init,
189};
190
Jonathan Neuschäfer8f06ce32017-11-20 01:56:44 +0100191static const struct cpu_device_id cpu_table[] = {
Alexandru Gagniuce644bad2012-08-07 19:38:32 -0500192 {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series
193 {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0
194 {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2
195 {0, 0},
196};
197
198static const struct cpu_driver driver __cpu_driver = {
199 .ops = &cpu_dev_ops,
200 .id_table = cpu_table,
201};