| Siyuan Wang | 8ff97b2 | 2012-10-28 18:19:38 +0800 | [diff] [blame^] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
| 15 | # You should have received a copy of the GNU General Public License |
| 16 | # along with this program; if not, write to the Free Software |
| 17 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | # |
| 19 | |
| 20 | if BOARD_SUPERMICRO_H8SCM |
| 21 | |
| 22 | config BOARD_SPECIFIC_OPTIONS |
| 23 | def_bool y |
| 24 | select ARCH_X86 |
| 25 | select CPU_AMD_AGESA_FAMILY15 |
| 26 | select CPU_AMD_SOCKET_C32 |
| 27 | select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX |
| 28 | select NORTHBRIDGE_AMD_AGESA_FAMILY15 |
| 29 | select NORTHBRIDGE_AMD_CIMX_RD890 |
| 30 | select SOUTHBRIDGE_AMD_CIMX_SB700 |
| 31 | select SUPERIO_WINBOND_W83627DHG |
| 32 | select SUPERIO_NUVOTON_WPCM450 |
| 33 | select DRIVERS_I2C_W83795 |
| 34 | select HAVE_OPTION_TABLE |
| 35 | select HAVE_PIRQ_TABLE |
| 36 | select HAVE_MP_TABLE |
| 37 | select HAVE_HARD_RESET |
| 38 | select SERIAL_CPU_INIT |
| 39 | select HAVE_ACPI_TABLES |
| 40 | select BOARD_ROMSIZE_KB_4096 |
| 41 | select TINY_BOOTBLOCK |
| 42 | |
| 43 | config MAINBOARD_DIR |
| 44 | string |
| 45 | default supermicro/h8scm |
| 46 | |
| 47 | config MAINBOARD_PART_NUMBER |
| 48 | string |
| 49 | default "H8SCM" |
| 50 | |
| 51 | config HW_MEM_HOLE_SIZEK |
| 52 | hex |
| 53 | default 0x200000 |
| 54 | |
| 55 | config MAX_CPUS |
| 56 | int |
| 57 | default 64 |
| 58 | |
| 59 | config MAX_PHYSICAL_CPUS |
| 60 | int |
| 61 | default 16 |
| 62 | |
| 63 | config HW_MEM_HOLE_SIZE_AUTO_INC |
| 64 | bool |
| 65 | default n |
| 66 | |
| 67 | config MEM_TRAIN_SEQ |
| 68 | int |
| 69 | default 2 |
| 70 | |
| 71 | config IRQ_SLOT_COUNT |
| 72 | int |
| 73 | default 11 |
| 74 | |
| 75 | config RAMTOP |
| 76 | hex |
| 77 | default 0x1000000 |
| 78 | |
| 79 | config HEAP_SIZE |
| 80 | hex |
| 81 | default 0xc0000 |
| 82 | |
| 83 | config STACK_SIZE |
| 84 | hex |
| 85 | default 0x10000 |
| 86 | |
| 87 | config RAMBASE |
| 88 | hex |
| 89 | default 0x200000 |
| 90 | |
| 91 | config SIO_PORT |
| 92 | hex |
| 93 | default 0x164E |
| 94 | help |
| 95 | though UARTs are on the NUVOTON BMC, port 0x164E |
| 96 | PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E |
| 97 | |
| 98 | config DRIVERS_PS2_KEYBOARD |
| 99 | bool |
| 100 | default y |
| 101 | |
| 102 | config WARNINGS_ARE_ERRORS |
| 103 | bool |
| 104 | default n |
| 105 | |
| 106 | config ONBOARD_VGA_IS_PRIMARY |
| 107 | bool |
| 108 | default y |
| 109 | |
| 110 | config VGA_BIOS |
| 111 | bool |
| 112 | default n |
| 113 | |
| 114 | config VGA_BIOS_ID |
| 115 | string |
| 116 | depends on VGA_BIOS |
| 117 | default "102b,0532" |
| 118 | |
| 119 | endif # BOARD_SUPERMICRO_H8SCM_FAM15 |