blob: 365da2faa6679bcf79a0d947a04ee4683d3710af [file] [log] [blame]
Subrata Banik6c4b5912017-11-07 16:10:05 +05301/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <device/device.h>
18#include <device/pci.h>
19#include <device/pci_ids.h>
20#include <device/spi.h>
21#include <intelblocks/fast_spi.h>
22#include <intelblocks/gspi.h>
23#include <intelblocks/spi.h>
24#include <soc/pci_devs.h>
25#include <spi-generic.h>
26
27const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
28 { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
Julius Wernercd49cce2019-03-05 16:53:33 -080029#if !ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI)
Subrata Banik6c4b5912017-11-07 16:10:05 +053030 { .ctrlr = &gspi_ctrlr, .bus_start = 1,
31 .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
32#endif
33};
34
35const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
36
37static int spi_dev_to_bus(struct device *dev)
38{
39 return spi_soc_devfn_to_bus(dev->path.pci.devfn);
40}
41
42static struct spi_bus_operations spi_bus_ops = {
43 .dev_to_bus = &spi_dev_to_bus,
44};
45
46static struct device_operations spi_dev_ops = {
Elyes HAOUAS1d191272018-11-27 12:23:48 +010047 .read_resources = pci_dev_read_resources,
48 .set_resources = pci_dev_set_resources,
49 .enable_resources = pci_dev_enable_resources,
50 .scan_bus = scan_generic_bus,
Subrata Banik6c4b5912017-11-07 16:10:05 +053051 .ops_spi_bus = &spi_bus_ops,
Subrata Banik6bbc91a2017-12-07 14:55:51 +053052 .ops_pci = &pci_dev_ops_pci,
Subrata Banik6c4b5912017-11-07 16:10:05 +053053};
54
55static const unsigned short pci_device_ids[] = {
56 PCI_DEVICE_ID_INTEL_SPT_SPI1,
57 PCI_DEVICE_ID_INTEL_SPT_SPI2,
58 PCI_DEVICE_ID_INTEL_SPT_SPI3,
59 PCI_DEVICE_ID_INTEL_APL_SPI0,
60 PCI_DEVICE_ID_INTEL_APL_SPI1,
61 PCI_DEVICE_ID_INTEL_APL_SPI2,
62 PCI_DEVICE_ID_INTEL_APL_HWSEQ_SPI,
63 PCI_DEVICE_ID_INTEL_GLK_SPI0,
64 PCI_DEVICE_ID_INTEL_GLK_SPI1,
65 PCI_DEVICE_ID_INTEL_GLK_SPI2,
66 PCI_DEVICE_ID_INTEL_CNL_SPI0,
67 PCI_DEVICE_ID_INTEL_CNL_SPI1,
68 PCI_DEVICE_ID_INTEL_CNL_SPI2,
69 PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI,
Lean Sheng Tan38c3ff72019-05-27 13:06:35 +080070 PCI_DEVICE_ID_INTEL_CNP_H_SPI0,
71 PCI_DEVICE_ID_INTEL_CNP_H_SPI1,
72 PCI_DEVICE_ID_INTEL_CNP_H_SPI2,
73 PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI,
Maxim Polyakov571d07d2019-08-22 13:11:32 +030074 PCI_DEVICE_ID_INTEL_LWB_SPI,
75 PCI_DEVICE_ID_INTEL_LWB_SPI_SUPER,
Aamir Bohra9eac0392018-06-30 12:07:04 +053076 PCI_DEVICE_ID_INTEL_ICP_SPI0,
77 PCI_DEVICE_ID_INTEL_ICP_SPI1,
78 PCI_DEVICE_ID_INTEL_ICP_SPI2,
79 PCI_DEVICE_ID_INTEL_ICP_HWSEQ_SPI,
Ronak Kanabarda7ffb482019-02-05 01:51:13 +053080 PCI_DEVICE_ID_INTEL_CMP_SPI0,
81 PCI_DEVICE_ID_INTEL_CMP_SPI1,
82 PCI_DEVICE_ID_INTEL_CMP_SPI2,
83 PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI,
Subrata Banik6c4b5912017-11-07 16:10:05 +053084 0
85};
86
87static const struct pci_driver pch_spi __pci_driver = {
88 .ops = &spi_dev_ops,
89 .vendor = PCI_VENDOR_ID_INTEL,
90 .devices = pci_device_ids,
91};