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Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001/*
2 * This file is part of the coreboot project.
3 *
Marshall Dawsone7d892c2016-10-08 14:49:41 -06004 * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/*
17 * ROMSIG At ROMBASE + 0x20000:
zbaoc3b0b722016-02-19 13:47:31 +080018 * 0 4 8 C
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080019 * +------------+---------------+----------------+------------+
20 * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
21 * +------------+---------------+----------------+------------+
zbaoc3b0b722016-02-19 13:47:31 +080022 * | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either
23 * +------------+---------------+ 2nd PSP directory or PSP COMBO directory
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080024 * EC ROM should be 64K aligned.
25 *
Zheng Bao4fcc9f22015-11-20 12:29:04 +080026 * PSP directory (Where "PSPDIR ADDR" points)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080027 * +------------+---------------+----------------+------------+
28 * | 'PSP$' | Fletcher | Count | Reserved |
29 * +------------+---------------+----------------+------------+
30 * | 0 | size | Base address | Reserved | Pubkey
31 * +------------+---------------+----------------+------------+
32 * | 1 | size | Base address | Reserved | Bootloader
33 * +------------+---------------+----------------+------------+
34 * | 8 | size | Base address | Reserved | Smu Firmware
35 * +------------+---------------+----------------+------------+
36 * | 3 | size | Base address | Reserved | Recovery Firmware
37 * +------------+---------------+----------------+------------+
38 * | |
39 * | |
40 * | Other PSP Firmware |
41 * | |
42 * | |
43 * +------------+---------------+----------------+------------+
Zheng Bao4fcc9f22015-11-20 12:29:04 +080044 *
zbaoc3b0b722016-02-19 13:47:31 +080045 * PSP Combo directory
Zheng Bao4fcc9f22015-11-20 12:29:04 +080046 * +------------+---------------+----------------+------------+
zbao6e2f3d12016-02-19 13:34:59 +080047 * | 'PSP2' | Fletcher | Count |Look up mode|
Zheng Bao4fcc9f22015-11-20 12:29:04 +080048 * +------------+---------------+----------------+------------+
zbaoc3a08a92016-03-02 14:47:27 +080049 * | R e s e r v e d |
50 * +------------+---------------+----------------+------------+
zbao6e2f3d12016-02-19 13:34:59 +080051 * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory
Zheng Bao4fcc9f22015-11-20 12:29:04 +080052 * +------------+---------------+----------------+------------+
zbao6e2f3d12016-02-19 13:34:59 +080053 * | ID-Sel | PSP ID | PSPDIR ADDR | | 3rd PSP directory
Zheng Bao4fcc9f22015-11-20 12:29:04 +080054 * +------------+---------------+----------------+------------+
55 * | |
56 * | Other PSP |
57 * | |
58 * +------------+---------------+----------------+------------+
59 *
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080060 */
61
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080062#include <fcntl.h>
63#include <errno.h>
64#include <stdio.h>
65#include <sys/stat.h>
66#include <sys/types.h>
67#include <unistd.h>
68#include <string.h>
69#include <stdlib.h>
70#include <getopt.h>
71
72#ifndef CONFIG_ROM_SIZE
73#define CONFIG_ROM_SIZE 0x400000
74#endif
75
Martin Roth60f15512016-11-08 09:55:01 -070076#define AMD_ROMSIG_OFFSET 0x20000
77#define MIN_ROM_KB 256
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080078
Martin Rothcd15bc82016-11-08 11:34:02 -070079#define ALIGN(val, by) (((val) + (by) - 1) & ~((by) - 1))
Marshall Dawson7c1e1422019-04-11 09:44:43 -060080#define _MAX(A, B) (((A) > (B)) ? (A) : (B))
81#define ERASE_ALIGNMENT 0x1000U
Marshall Dawson2794a862019-03-04 16:53:15 -070082#define TABLE_ALIGNMENT 0x1000U
83#define BLOB_ALIGNMENT 0x100U
Marshall Dawson24f73d42019-04-01 10:48:43 -060084#define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT)
Marshall Dawson7c1e1422019-04-11 09:44:43 -060085#define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080086
Marshall Dawsonef79fcc2019-04-01 10:16:41 -060087#define DEFAULT_SOFT_FUSE_CHAIN "0x1"
88
Marshall Dawson239286c2019-02-23 16:42:46 -070089#define EMBEDDED_FW_SIGNATURE 0x55aa55aa
Marshall Dawson24f73d42019-04-01 10:48:43 -060090#define PSP_COOKIE 0x50535024 /* 'PSP$' */
91#define PSPL2_COOKIE 0x324c5024 /* '2LP$' */
92#define PSP2_COOKIE 0x50535032 /* 'PSP2' */
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -060093#define BDT1_COOKIE 0x44484224 /* 'DHB$ */
94#define BDT2_COOKIE 0x324c4224 /* '2LB$ */
Marshall Dawson239286c2019-02-23 16:42:46 -070095
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080096/*
Marshall Dawson0e02ce82019-03-04 16:50:37 -070097 * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP
98 * can support an optional "combo" implementation. If the PSP sees the
99 * PSP2 cookie, it interprets the table as a roadmap to additional PSP
100 * tables. Using this, support for multiple product generations may be
101 * built into one image. If the PSP$ cookie is found, the table is a
102 * normal directory table.
103 *
104 * Modern generations supporting the combo directories require the
105 * pointer to be at offset 0x14 of the Embedded Firmware Structure,
106 * regardless of the type of directory used. The --combo-capable
107 * argument enforces this placement.
108 *
109 * TODO: Future work may require fully implementing the PSP_COMBO feature.
zbaoc3b0b722016-02-19 13:47:31 +0800110 */
Marshall Dawson0e02ce82019-03-04 16:50:37 -0700111#define PSP_COMBO 0
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800112
Idwer Volleringa682fc82019-12-16 15:33:12 +0100113#if defined(__GLIBC__)
Marshall Dawson239286c2019-02-23 16:42:46 -0700114typedef unsigned long long int uint64_t;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800115typedef unsigned int uint32_t;
116typedef unsigned char uint8_t;
117typedef unsigned short uint16_t;
Idwer Volleringa682fc82019-12-16 15:33:12 +0100118#endif
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800119
120/*
121 * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3.
122 * The checksum field of the passed PDU does not need to be reset to zero.
123 *
124 * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of
125 * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an
126 * alternative to cyclical redundancy checks because it provides error-
127 * detection properties similar to cyclical redundancy checks but at the
128 * cost of a simple summation technique. Its characteristics were first
129 * published in IEEE Transactions on Communications in January 1982. One
130 * version has been adopted by ISO for use in the class-4 transport layer
131 * of the network protocol.
132 *
133 * This program expects:
134 * stdin: The input file to compute a checksum for. The input file
135 * not be longer than 256 bytes.
136 * stdout: Copied from the input file with the Fletcher's Checksum
137 * inserted 8 bytes after the beginning of the file.
138 * stderr: Used to print out error messages.
139 */
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700140static uint32_t fletcher32(const void *data, int length)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800141{
142 uint32_t c0;
143 uint32_t c1;
144 uint32_t checksum;
145 int index;
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700146 const uint16_t *pptr = data;
147
148 length /= 2;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800149
150 c0 = 0xFFFF;
151 c1 = 0xFFFF;
152
Marshall Dawsonb85ddc52019-07-23 07:24:30 -0600153 while (length) {
154 index = length >= 359 ? 359 : length;
155 length -= index;
156 do {
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800157 c0 += *(pptr++);
158 c1 += c0;
Marshall Dawsonb85ddc52019-07-23 07:24:30 -0600159 } while (--index);
160 c0 = (c0 & 0xFFFF) + (c0 >> 16);
161 c1 = (c1 & 0xFFFF) + (c1 >> 16);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800162 }
163
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700164 /* Sums[0,1] mod 64K + overflow */
165 c0 = (c0 & 0xFFFF) + (c0 >> 16);
166 c1 = (c1 & 0xFFFF) + (c1 >> 16);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800167 checksum = (c1 << 16) | c0;
168
169 return checksum;
170}
171
Martin Roth8806f7f2016-11-08 10:44:18 -0700172static void usage(void)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800173{
Martin Roth0e940622016-11-08 10:37:53 -0700174 printf("amdfwtool: Create AMD Firmware combination\n");
175 printf("Usage: amdfwtool [options] -f <size> -o <filename>\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600176 printf("-x | --xhci <FILE> Add XHCI blob\n");
177 printf("-i | --imc <FILE> Add IMC blob\n");
178 printf("-g | --gec <FILE> Add GEC blob\n");
Martin Roth0e940622016-11-08 10:37:53 -0700179
180 printf("\nPSP options:\n");
Marshall Dawson67d868d2019-02-28 11:43:40 -0700181 printf("-A | --combo-capable Place PSP directory pointer at Embedded Firmware\n");
182 printf(" offset able to support combo directory\n");
Marshall Dawson24f73d42019-04-01 10:48:43 -0600183 printf("-M | --multilevel Generate primary and secondary tables\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600184 printf("-p | --pubkey <FILE> Add pubkey\n");
185 printf("-b | --bootloader <FILE> Add bootloader\n");
Marshall Dawsondbae6322019-03-04 10:31:03 -0700186 printf("-S | --subprogram <number> Sets subprogram field for the next firmware\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600187 printf("-s | --smufirmware <FILE> Add smufirmware\n");
188 printf("-r | --recovery <FILE> Add recovery\n");
189 printf("-k | --rtmpubkey <FILE> Add rtmpubkey\n");
190 printf("-c | --secureos <FILE> Add secureos\n");
191 printf("-n | --nvram <FILE> Add nvram\n");
192 printf("-d | --securedebug <FILE> Add securedebug\n");
193 printf("-t | --trustlets <FILE> Add trustlets\n");
194 printf("-u | --trustletkey <FILE> Add trustletkey\n");
195 printf("-w | --smufirmware2 <FILE> Add smufirmware2\n");
196 printf("-m | --smuscs <FILE> Add smuscs\n");
Marshall Dawsonef79fcc2019-04-01 10:16:41 -0600197 printf("-T | --soft-fuse <HEX_VAL> Override default soft fuse values\n");
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600198 printf("-z | --abl-image <FILE> Add AGESA Binary\n");
199 printf("-J | --sec-gasket <FILE> Add security gasket\n");
200 printf("-B | --mp2-fw <FILE> Add MP2 firmware\n");
201 printf("-N | --secdebug <FILE> Add secure unlock image\n");
202 printf("-U | --token-unlock Reserve space for debug token\n");
203 printf("-K | --drv-entry-pts <FILE> Add PSP driver entry points\n");
204 printf("-L | --ikek <FILE> Add Wrapped iKEK\n");
205 printf("-Y | --s0i3drv <FILE> Add s0i3 driver\n");
Martin Rothd3ce8c82019-07-13 20:13:07 -0600206 printf("-Z | --verstage <FILE> Add verstage\n");
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600207 printf("\nBIOS options:\n");
208 printf("-I | --instance <number> Sets instance field for the next BIOS firmware\n");
209 printf("-a | --apcb <FILE> Add AGESA PSP customization block\n");
210 printf("-Q | --apob-base <HEX_VAL> Destination for AGESA PSP output block\n");
211 printf("-F | --apob-nv-base <HEX_VAL> Location of S3 resume data\n");
212 printf("-H | --apob-nv-size <HEX_VAL> Size of S3 resume data\n");
213 printf("-y | --pmu-inst <FILE> Add PMU firmware instruction portion\n");
214 printf("-G | --pmu-data <FILE> Add PMU firmware data portion\n");
Martin Rothec933132019-07-13 20:03:34 -0600215 printf("-O | --ucode <FILE> Add microcode patch\n");
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600216 printf("-X | --mp2-config <FILE> Add MP2 configuration\n");
217 printf("-V | --bios-bin <FILE> Add compressed image; auto source address\n");
218 printf("-e | --bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n");
219 printf("-v | --bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n");
220 printf("-j | --bios-uncomp-size <HEX> Uncompressed size of BIOS image\n");
Martin Roth0e940622016-11-08 10:37:53 -0700221 printf("\n-o | --output <filename> output filename\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600222 printf("-f | --flashsize <HEX_VAL> ROM size in bytes\n");
223 printf(" size must be larger than %dKB\n",
Martin Roth0e940622016-11-08 10:37:53 -0700224 MIN_ROM_KB);
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600225 printf(" and must a multiple of 1024\n");
Martin Roth0d3b1182017-10-03 14:16:04 -0600226 printf("-l | --location Location of Directory\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600227 printf("-h | --help show this help\n");
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800228}
229
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600230typedef enum _amd_bios_type {
231 AMD_BIOS_APCB = 0x60,
232 AMD_BIOS_APOB = 0x61,
233 AMD_BIOS_BIN = 0x62,
234 AMD_BIOS_APOB_NV = 0x63,
235 AMD_BIOS_PMUI = 0x64,
236 AMD_BIOS_PMUD = 0x65,
237 AMD_BIOS_UCODE = 0x66,
238 AMD_BIOS_APCB_BK = 0x68,
239 AMD_BIOS_MP2_CFG = 0x6a,
240 AMD_BIOS_L2_PTR = 0x70,
241 AMD_BIOS_INVALID,
242} amd_bios_type;
243
244#define BDT_LVL1 0x1
245#define BDT_LVL2 0x2
246#define BDT_BOTH (BDT_LVL1 | BDT_LVL2)
247typedef struct _amd_bios_entry {
248 amd_bios_type type;
249 int region_type;
250 int reset;
251 int copy;
252 int ro;
253 int zlib;
254 int inst;
255 int subpr;
256 uint64_t src;
257 uint64_t dest;
258 size_t size;
259 char *filename;
260 int level;
261} amd_bios_entry;
262
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800263typedef enum _amd_fw_type {
264 AMD_FW_PSP_PUBKEY = 0,
265 AMD_FW_PSP_BOOTLOADER = 1,
266 AMD_FW_PSP_SMU_FIRMWARE = 8,
267 AMD_FW_PSP_RECOVERY = 3,
268 AMD_FW_PSP_RTM_PUBKEY = 5,
269 AMD_FW_PSP_SECURED_OS = 2,
270 AMD_FW_PSP_NVRAM = 4,
271 AMD_FW_PSP_SECURED_DEBUG = 9,
272 AMD_FW_PSP_TRUSTLETS = 12,
273 AMD_FW_PSP_TRUSTLETKEY = 13,
274 AMD_FW_PSP_SMU_FIRMWARE2 = 18,
275 AMD_PSP_FUSE_CHAIN = 11,
276 AMD_FW_PSP_SMUSCS = 95,
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600277 AMD_DEBUG_UNLOCK = 0x13,
278 AMD_WRAPPED_IKEK = 0x21,
279 AMD_TOKEN_UNLOCK = 0x22,
280 AMD_SEC_GASKET = 0x24,
281 AMD_MP2_FW = 0x25,
282 AMD_DRIVER_ENTRIES = 0x28,
283 AMD_S0I3_DRIVER = 0x2d,
284 AMD_ABL0 = 0x30,
285 AMD_ABL1 = 0x31,
286 AMD_ABL2 = 0x32,
287 AMD_ABL3 = 0x33,
288 AMD_ABL4 = 0x34,
289 AMD_ABL5 = 0x35,
290 AMD_ABL6 = 0x36,
291 AMD_ABL7 = 0x37,
292 AMD_FW_PSP_WHITELIST = 0x3a,
Marshall Dawson24f73d42019-04-01 10:48:43 -0600293 AMD_FW_L2_PTR = 0x40,
Martin Rothd3ce8c82019-07-13 20:13:07 -0600294 AMD_FW_PSP_VERSTAGE = 0x52,
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800295 AMD_FW_IMC,
296 AMD_FW_GEC,
297 AMD_FW_XHCI,
zbaoc3a08a92016-03-02 14:47:27 +0800298 AMD_FW_INVALID,
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800299} amd_fw_type;
300
Marshall Dawson24f73d42019-04-01 10:48:43 -0600301#define PSP_LVL1 0x1
302#define PSP_LVL2 0x2
303#define PSP_BOTH (PSP_LVL1 | PSP_LVL2)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800304typedef struct _amd_fw_entry {
305 amd_fw_type type;
Marshall Dawsondbae6322019-03-04 10:31:03 -0700306 uint8_t subprog;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800307 char *filename;
Marshall Dawson24f73d42019-04-01 10:48:43 -0600308 int level;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -0600309 uint64_t other;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800310} amd_fw_entry;
311
Martin Roth8806f7f2016-11-08 10:44:18 -0700312static amd_fw_entry amd_psp_fw_table[] = {
Marshall Dawson24f73d42019-04-01 10:48:43 -0600313 { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH },
314 { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH },
315 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH },
316 { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 },
317 { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH },
318 { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 },
319 { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 },
320 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH },
321 { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 },
322 { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 },
323 { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 },
324 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH },
325 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH },
326 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH },
327 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH },
328 { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH },
329 { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600330 { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 },
331 { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH },
332 { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH },
333 { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH },
334 { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH },
335 { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 },
336 { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 },
337 { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 },
338 { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 },
339 { .type = AMD_ABL0, .level = PSP_BOTH },
340 { .type = AMD_ABL1, .level = PSP_BOTH },
341 { .type = AMD_ABL2, .level = PSP_BOTH },
342 { .type = AMD_ABL3, .level = PSP_BOTH },
343 { .type = AMD_ABL4, .level = PSP_BOTH },
344 { .type = AMD_ABL5, .level = PSP_BOTH },
345 { .type = AMD_ABL6, .level = PSP_BOTH },
346 { .type = AMD_ABL7, .level = PSP_BOTH },
Marshall Dawson24f73d42019-04-01 10:48:43 -0600347 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH },
348 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600349 { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 },
Martin Rothd3ce8c82019-07-13 20:13:07 -0600350 { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH },
zbaoc3a08a92016-03-02 14:47:27 +0800351 { .type = AMD_FW_INVALID },
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800352};
353
Martin Roth8806f7f2016-11-08 10:44:18 -0700354static amd_fw_entry amd_fw_table[] = {
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800355 { .type = AMD_FW_XHCI },
356 { .type = AMD_FW_IMC },
357 { .type = AMD_FW_GEC },
zbaoc3a08a92016-03-02 14:47:27 +0800358 { .type = AMD_FW_INVALID },
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800359};
360
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600361static amd_bios_entry amd_bios_table[] = {
Marshall Dawson0581bf62019-09-25 11:03:53 -0600362 { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH },
363 { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH },
364 { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH },
365 { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH },
366 { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH },
Marshall Dawson2dd3b5c2020-01-03 17:57:48 -0700367 { .type = AMD_BIOS_APCB_BK, .inst = 0, .level = BDT_BOTH },
368 { .type = AMD_BIOS_APCB_BK, .inst = 1, .level = BDT_BOTH },
369 { .type = AMD_BIOS_APCB_BK, .inst = 2, .level = BDT_BOTH },
370 { .type = AMD_BIOS_APCB_BK, .inst = 3, .level = BDT_BOTH },
371 { .type = AMD_BIOS_APCB_BK, .inst = 4, .level = BDT_BOTH },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600372 { .type = AMD_BIOS_APOB, .level = BDT_BOTH },
373 { .type = AMD_BIOS_BIN,
374 .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH },
375 { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 },
376 { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH },
377 { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH },
378 { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH },
379 { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH },
380 { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH },
381 { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH },
382 { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH },
383 { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH },
384 { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 },
385 { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 },
386 { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 },
387 { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 },
388 { .type = AMD_BIOS_INVALID },
389};
390
Marshall Dawson239286c2019-02-23 16:42:46 -0700391typedef struct _embedded_firmware {
392 uint32_t signature; /* 0x55aa55aa */
393 uint32_t imc_entry;
394 uint32_t gec_entry;
395 uint32_t xhci_entry;
396 uint32_t psp_entry;
397 uint32_t comboable;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600398 uint32_t bios0_entry; /* todo: add way to select correct entry */
399 uint32_t bios1_entry;
Marshall Dawson94f24922019-09-28 08:49:09 -0600400 uint32_t bios2_entry;
401 uint32_t reserved[0x2c]; /* 0x24 - 0x4f */
Marshall Dawson239286c2019-02-23 16:42:46 -0700402} __attribute__((packed, aligned(16))) embedded_firmware;
403
404typedef struct _psp_directory_header {
405 uint32_t cookie;
406 uint32_t checksum;
407 uint32_t num_entries;
408 uint32_t reserved;
409} __attribute__((packed, aligned(16))) psp_directory_header;
410
411typedef struct _psp_directory_entry {
Marshall Dawsondbae6322019-03-04 10:31:03 -0700412 uint8_t type;
413 uint8_t subprog;
414 uint16_t rsvd;
Marshall Dawson239286c2019-02-23 16:42:46 -0700415 uint32_t size;
416 uint64_t addr; /* or a value in some cases */
417} __attribute__((packed)) psp_directory_entry;
418
419typedef struct _psp_directory_table {
420 psp_directory_header header;
421 psp_directory_entry entries[];
422} __attribute__((packed)) psp_directory_table;
423
Marshall Dawson2794a862019-03-04 16:53:15 -0700424#define MAX_PSP_ENTRIES 0x1f
425
Marshall Dawson239286c2019-02-23 16:42:46 -0700426typedef struct _psp_combo_header {
427 uint32_t cookie;
428 uint32_t checksum;
429 uint32_t num_entries;
430 uint32_t lookup;
431 uint64_t reserved[2];
432} __attribute__((packed, aligned(16))) psp_combo_header;
433
434typedef struct _psp_combo_entry {
435 uint32_t id_sel;
436 uint32_t id;
437 uint64_t lvl2_addr;
438} __attribute__((packed)) psp_combo_entry;
439
440typedef struct _psp_combo_directory {
441 psp_combo_header header;
442 psp_combo_entry entries[];
443} __attribute__((packed)) psp_combo_directory;
444
Marshall Dawson2794a862019-03-04 16:53:15 -0700445#define MAX_COMBO_ENTRIES 1
446
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600447typedef struct _bios_directory_hdr {
448 uint32_t cookie;
449 uint32_t checksum;
450 uint32_t num_entries;
451 uint32_t reserved;
452} __attribute__((packed, aligned(16))) bios_directory_hdr;
453
454typedef struct _bios_directory_entry {
455 uint8_t type;
456 uint8_t region_type;
457 int reset:1;
458 int copy:1;
459 int ro:1;
460 int compressed:1;
461 int inst:4;
462 uint8_t subprog; /* b[7:3] reserved */
463 uint32_t size;
464 uint64_t source;
465 uint64_t dest;
466} __attribute__((packed)) bios_directory_entry;
467
468typedef struct _bios_directory_table {
469 bios_directory_hdr header;
470 bios_directory_entry entries[];
471} bios_directory_table;
472
473#define MAX_BIOS_ENTRIES 0x1f
474
Marshall Dawson2794a862019-03-04 16:53:15 -0700475typedef struct _context {
476 char *rom; /* target buffer, size of flash device */
477 uint32_t rom_size; /* size of flash device */
478 uint32_t current; /* pointer within flash & proxy buffer */
479} context;
480
481#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1)
482#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset))
483#define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current)
484#define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))
485#define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current)
486#define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom))
487#define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current)
488
Marshall Dawson24f73d42019-04-01 10:48:43 -0600489static void *new_psp_dir(context *ctx, int multi)
Marshall Dawson2794a862019-03-04 16:53:15 -0700490{
491 void *ptr;
492
Marshall Dawson24f73d42019-04-01 10:48:43 -0600493 /*
494 * Force both onto boundary when multi. Primary table is after
495 * updatable table, so alignment ensures primary can stay intact
496 * if secondary is reprogrammed.
497 */
498 if (multi)
499 ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT);
500 else
501 ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
502
Marshall Dawson2794a862019-03-04 16:53:15 -0700503 ptr = BUFF_CURRENT(*ctx);
504 ctx->current += sizeof(psp_directory_header)
505 + MAX_PSP_ENTRIES * sizeof(psp_directory_entry);
506 return ptr;
507}
508
Martin Rothec933132019-07-13 20:03:34 -0600509#if PSP_COMBO
Marshall Dawson2794a862019-03-04 16:53:15 -0700510static void *new_combo_dir(context *ctx)
511{
512 void *ptr;
513
514 ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
515 ptr = BUFF_CURRENT(*ctx);
516 ctx->current += sizeof(psp_combo_header)
517 + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry);
518 return ptr;
519}
Martin Rothec933132019-07-13 20:03:34 -0600520#endif
Marshall Dawson2794a862019-03-04 16:53:15 -0700521
Marshall Dawsona378c222019-03-04 16:52:07 -0700522static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800523{
Marshall Dawson24f73d42019-04-01 10:48:43 -0600524 psp_combo_directory *cdir = directory;
525 psp_directory_table *dir = directory;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600526 bios_directory_table *bdir = directory;
Marshall Dawson24f73d42019-04-01 10:48:43 -0600527
528 if (!count)
529 return;
530
531 switch (cookie) {
532 case PSP2_COOKIE:
Marshall Dawsona378c222019-03-04 16:52:07 -0700533 /* caller is responsible for lookup mode */
Marshall Dawsona378c222019-03-04 16:52:07 -0700534 cdir->header.cookie = cookie;
535 cdir->header.num_entries = count;
536 cdir->header.reserved[0] = 0;
537 cdir->header.reserved[1] = 0;
538 /* checksum everything that comes after the Checksum field */
539 cdir->header.checksum = fletcher32(&cdir->header.num_entries,
540 count * sizeof(psp_combo_entry)
541 + sizeof(cdir->header.num_entries)
542 + sizeof(cdir->header.lookup)
543 + 2 * sizeof(cdir->header.reserved[0]));
Marshall Dawson24f73d42019-04-01 10:48:43 -0600544 break;
545 case PSP_COOKIE:
546 case PSPL2_COOKIE:
Marshall Dawsona378c222019-03-04 16:52:07 -0700547 dir->header.cookie = cookie;
548 dir->header.num_entries = count;
549 dir->header.reserved = 0;
550 /* checksum everything that comes after the Checksum field */
551 dir->header.checksum = fletcher32(&dir->header.num_entries,
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700552 count * sizeof(psp_directory_entry)
Marshall Dawsona378c222019-03-04 16:52:07 -0700553 + sizeof(dir->header.num_entries)
554 + sizeof(dir->header.reserved));
Marshall Dawson24f73d42019-04-01 10:48:43 -0600555 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600556 case BDT1_COOKIE:
557 case BDT2_COOKIE:
558 bdir->header.cookie = cookie;
559 bdir->header.num_entries = count;
560 bdir->header.reserved = 0;
561 /* checksum everything that comes after the Checksum field */
562 bdir->header.checksum = fletcher32(&bdir->header.num_entries,
563 count * sizeof(bios_directory_entry)
564 + sizeof(bdir->header.num_entries)
565 + sizeof(bdir->header.reserved));
566 break;
Marshall Dawsona378c222019-03-04 16:52:07 -0700567 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800568}
569
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700570static ssize_t copy_blob(void *dest, const char *src_file, size_t room)
571{
572 int fd;
573 struct stat fd_stat;
574 ssize_t bytes;
575
576 fd = open(src_file, O_RDONLY);
577 if (fd < 0) {
578 printf("Error: %s\n", strerror(errno));
579 return -1;
580 }
581
582 if (fstat(fd, &fd_stat)) {
583 printf("fstat error: %s\n", strerror(errno));
Jacob Garber967f8622019-07-02 10:35:10 -0600584 close(fd);
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700585 return -2;
586 }
587
588 if (fd_stat.st_size > room) {
589 printf("Error: %s will not fit. Exiting.\n", src_file);
Jacob Garber967f8622019-07-02 10:35:10 -0600590 close(fd);
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700591 return -3;
592 }
593
594 bytes = read(fd, dest, (size_t)fd_stat.st_size);
595 close(fd);
596 if (bytes != (ssize_t)fd_stat.st_size) {
597 printf("Error while reading %s\n", src_file);
598 return -4;
599 }
600
601 return bytes;
602}
603
Marshall Dawson2794a862019-03-04 16:53:15 -0700604static void integrate_firmwares(context *ctx,
Marshall Dawson239286c2019-02-23 16:42:46 -0700605 embedded_firmware *romsig,
Marshall Dawson2794a862019-03-04 16:53:15 -0700606 amd_fw_entry *fw_table)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800607{
Richard Spiegel137484d2018-01-17 10:23:19 -0700608 ssize_t bytes;
zbaoc3a08a92016-03-02 14:47:27 +0800609 int i;
Marshall Dawson2794a862019-03-04 16:53:15 -0700610
611 ctx->current += sizeof(embedded_firmware);
612 ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800613
Martin Rothcd15bc82016-11-08 11:34:02 -0700614 for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
zbaoc3a08a92016-03-02 14:47:27 +0800615 if (fw_table[i].filename != NULL) {
zbaoc3a08a92016-03-02 14:47:27 +0800616 switch (fw_table[i].type) {
617 case AMD_FW_IMC:
Marshall Dawson2794a862019-03-04 16:53:15 -0700618 ctx->current = ALIGN(ctx->current, 0x10000U);
619 romsig->imc_entry = RUN_CURRENT(*ctx);
zbaoc3a08a92016-03-02 14:47:27 +0800620 break;
621 case AMD_FW_GEC:
Marshall Dawson2794a862019-03-04 16:53:15 -0700622 romsig->gec_entry = RUN_CURRENT(*ctx);
zbaoc3a08a92016-03-02 14:47:27 +0800623 break;
624 case AMD_FW_XHCI:
Marshall Dawson2794a862019-03-04 16:53:15 -0700625 romsig->xhci_entry = RUN_CURRENT(*ctx);
zbaoc3a08a92016-03-02 14:47:27 +0800626 break;
627 default:
628 /* Error */
629 break;
630 }
631
Marshall Dawson2794a862019-03-04 16:53:15 -0700632 bytes = copy_blob(BUFF_CURRENT(*ctx),
633 fw_table[i].filename, BUFF_ROOM(*ctx));
Marshall Dawson02bd7732019-03-13 14:43:17 -0600634 if (bytes < 0) {
Marshall Dawson2794a862019-03-04 16:53:15 -0700635 free(ctx->rom);
Martin Roth60f15512016-11-08 09:55:01 -0700636 exit(1);
637 }
638
Marshall Dawson2794a862019-03-04 16:53:15 -0700639 ctx->current = ALIGN(ctx->current + bytes,
640 BLOB_ALIGNMENT);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800641 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800642 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800643}
644
Marshall Dawson2794a862019-03-04 16:53:15 -0700645static void integrate_psp_firmwares(context *ctx,
Marshall Dawson239286c2019-02-23 16:42:46 -0700646 psp_directory_table *pspdir,
Marshall Dawson24f73d42019-04-01 10:48:43 -0600647 psp_directory_table *pspdir2,
648 amd_fw_entry *fw_table,
649 uint32_t cookie)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800650{
Richard Spiegel137484d2018-01-17 10:23:19 -0700651 ssize_t bytes;
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700652 unsigned int i, count;
Marshall Dawson24f73d42019-04-01 10:48:43 -0600653 int level;
654
655 /* This function can create a primary table, a secondary table, or a
656 * flattened table which contains all applicable types. These if-else
657 * statements infer what the caller intended. If a 2nd-level cookie
658 * is passed, clearly a 2nd-level table is intended. However, a
659 * 1st-level cookie may indicate level 1 or flattened. If the caller
660 * passes a pointer to a 2nd-level table, then assume not flat.
661 */
662 if (cookie == PSPL2_COOKIE)
663 level = PSP_LVL2;
664 else if (pspdir2)
665 level = PSP_LVL1;
666 else
667 level = PSP_BOTH;
Marshall Dawson2794a862019-03-04 16:53:15 -0700668
669 ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800670
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700671 for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
Marshall Dawson24f73d42019-04-01 10:48:43 -0600672 if (!(fw_table[i].level & level))
673 continue;
674
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600675 if (fw_table[i].type == AMD_TOKEN_UNLOCK) {
676 if (!fw_table[i].other)
677 continue;
678 ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
679 pspdir->entries[count].type = fw_table[i].type;
680 pspdir->entries[count].size = 4096; /* TODO: doc? */
681 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
682 pspdir->entries[count].subprog = fw_table[i].subprog;
683 pspdir->entries[count].rsvd = 0;
684 ctx->current = ALIGN(ctx->current + 4096, 0x100U);
685 count++;
686 } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) {
Marshall Dawson239286c2019-02-23 16:42:46 -0700687 pspdir->entries[count].type = fw_table[i].type;
Marshall Dawsondbae6322019-03-04 10:31:03 -0700688 pspdir->entries[count].subprog = fw_table[i].subprog;
689 pspdir->entries[count].rsvd = 0;
Marshall Dawson239286c2019-02-23 16:42:46 -0700690 pspdir->entries[count].size = 0xFFFFFFFF;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -0600691 pspdir->entries[count].addr = fw_table[i].other;
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700692 count++;
Marshall Dawson7c1e1422019-04-11 09:44:43 -0600693 } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) {
694 if (fw_table[i].filename == NULL)
695 continue;
696 /* TODO: Add a way to reserve for NVRAM without
697 * requiring a filename. This isn't a feature used
698 * by coreboot systems, so priority is very low.
699 */
700 ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
701 bytes = copy_blob(BUFF_CURRENT(*ctx),
702 fw_table[i].filename, BUFF_ROOM(*ctx));
703 if (bytes <= 0) {
704 free(ctx->rom);
705 exit(1);
706 }
707
708 pspdir->entries[count].type = fw_table[i].type;
709 pspdir->entries[count].subprog = fw_table[i].subprog;
710 pspdir->entries[count].rsvd = 0;
711 pspdir->entries[count].size = ALIGN(bytes,
712 ERASE_ALIGNMENT);
713 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
714
715 ctx->current = ALIGN(ctx->current + bytes,
716 BLOB_ERASE_ALIGNMENT);
717 count++;
zbaoc3a08a92016-03-02 14:47:27 +0800718 } else if (fw_table[i].filename != NULL) {
Marshall Dawson2794a862019-03-04 16:53:15 -0700719 bytes = copy_blob(BUFF_CURRENT(*ctx),
720 fw_table[i].filename, BUFF_ROOM(*ctx));
Marshall Dawson02bd7732019-03-13 14:43:17 -0600721 if (bytes < 0) {
Marshall Dawson2794a862019-03-04 16:53:15 -0700722 free(ctx->rom);
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700723 exit(1);
724 }
725
Marshall Dawson239286c2019-02-23 16:42:46 -0700726 pspdir->entries[count].type = fw_table[i].type;
Marshall Dawsondbae6322019-03-04 10:31:03 -0700727 pspdir->entries[count].subprog = fw_table[i].subprog;
728 pspdir->entries[count].rsvd = 0;
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700729 pspdir->entries[count].size = (uint32_t)bytes;
Marshall Dawson2794a862019-03-04 16:53:15 -0700730 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800731
Marshall Dawson2794a862019-03-04 16:53:15 -0700732 ctx->current = ALIGN(ctx->current + bytes,
733 BLOB_ALIGNMENT);
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700734 count++;
zbaoc3a08a92016-03-02 14:47:27 +0800735 } else {
736 /* This APU doesn't have this firmware. */
737 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800738 }
Marshall Dawson2794a862019-03-04 16:53:15 -0700739
Marshall Dawson24f73d42019-04-01 10:48:43 -0600740 if (pspdir2) {
741 pspdir->entries[count].type = AMD_FW_L2_PTR;
742 pspdir->entries[count].subprog = 0;
743 pspdir->entries[count].rsvd = 0;
744 pspdir->entries[count].size = sizeof(pspdir2->header)
745 + pspdir2->header.num_entries
746 * sizeof(psp_directory_entry);
747
748 pspdir->entries[count].addr = BUFF_TO_RUN(*ctx, pspdir2);
749 count++;
750 }
751
Marshall Dawson2794a862019-03-04 16:53:15 -0700752 if (count > MAX_PSP_ENTRIES) {
753 printf("Error: PSP entries exceed max allowed items\n");
754 free(ctx->rom);
755 exit(1);
756 }
757
Marshall Dawson24f73d42019-04-01 10:48:43 -0600758 fill_dir_header(pspdir, count, cookie);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800759}
760
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600761static void *new_bios_dir(context *ctx, int multi)
762{
763 void *ptr;
764
765 /*
766 * Force both onto boundary when multi. Primary table is after
767 * updatable table, so alignment ensures primary can stay intact
768 * if secondary is reprogrammed.
769 */
770 if (multi)
771 ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT);
772 else
773 ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
774 ptr = BUFF_CURRENT(*ctx);
775 ctx->current += sizeof(bios_directory_hdr)
776 + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry);
777 return ptr;
778}
779
780static int locate_bdt2_bios(bios_directory_table *level2,
781 uint64_t *source, uint32_t *size)
782{
783 int i;
784
785 *source = 0;
786 *size = 0;
787 if (!level2)
788 return 0;
789
790 for (i = 0 ; i < level2->header.num_entries ; i++) {
791 if (level2->entries[i].type == AMD_BIOS_BIN) {
792 *source = level2->entries[i].source;
793 *size = level2->entries[i].size;
794 return 1;
795 }
796 }
797 return 0;
798}
799
800static int have_bios_tables(amd_bios_entry *table)
801{
802 int i;
803
804 for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) {
805 if (table[i].level & BDT_LVL1 && table[i].filename)
806 return 1;
807 }
808 return 0;
809}
810
Marshall Dawsonc4a8c482020-01-21 17:17:59 -0700811static int find_bios_entry(amd_bios_type type)
812{
813 int i;
814
815 for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) {
816 if (amd_bios_table[i].type == type)
817 return i;
818 }
819 return -1;
820}
821
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600822static void integrate_bios_firmwares(context *ctx,
823 bios_directory_table *biosdir,
824 bios_directory_table *biosdir2,
825 amd_bios_entry *fw_table,
826 uint32_t cookie)
827{
828 ssize_t bytes;
Martin Rothec933132019-07-13 20:03:34 -0600829 unsigned int i, count;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600830 int level;
Marshall Dawsonc4a8c482020-01-21 17:17:59 -0700831 int apob_idx;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600832
833 /* This function can create a primary table, a secondary table, or a
834 * flattened table which contains all applicable types. These if-else
835 * statements infer what the caller intended. If a 2nd-level cookie
836 * is passed, clearly a 2nd-level table is intended. However, a
837 * 1st-level cookie may indicate level 1 or flattened. If the caller
838 * passes a pointer to a 2nd-level table, then assume not flat.
839 */
840 if (cookie == BDT2_COOKIE)
841 level = BDT_LVL2;
842 else if (biosdir2)
843 level = BDT_LVL1;
844 else
845 level = BDT_BOTH;
846
847 ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
848
849 for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) {
850 if (!(fw_table[i].level & level))
851 continue;
852 if (fw_table[i].filename == NULL && (
853 fw_table[i].type != AMD_BIOS_APOB &&
854 fw_table[i].type != AMD_BIOS_APOB_NV &&
855 fw_table[i].type != AMD_BIOS_L2_PTR &&
856 fw_table[i].type != AMD_BIOS_BIN))
857 continue;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600858
859 /* BIOS Directory items may have additional requirements */
860
861 /* APOB_NV must have a size if it has a source */
862 if (fw_table[i].type == AMD_BIOS_APOB_NV && fw_table[i].src) {
863 if (!fw_table[i].size) {
864 printf("Error: APOB NV address provided, but no size\n");
865 free(ctx->rom);
866 exit(1);
867 }
868 }
Marshall Dawsonc4a8c482020-01-21 17:17:59 -0700869 /* APOB_NV needs a size, else no choice but to skip the item */
870 if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size) {
871 /* Attempt to determine whether this is an error */
872 apob_idx = find_bios_entry(AMD_BIOS_APOB);
873 if (apob_idx < 0 || !fw_table[apob_idx].dest) {
874 /* APOV NV not expected to be used */
875 continue;
876 } else {
877 printf("Error: APOB NV must have a size\n");
878 free(ctx->rom);
879 exit(1);
880 }
881 }
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600882
883 /* APOB_DATA needs destination */
884 if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) {
885 printf("Error: APOB destination not provided\n");
886 free(ctx->rom);
887 exit(1);
888 }
889
890 /* BIOS binary must have destination and uncompressed size. If
891 * no filename given, then user must provide a source address.
892 */
893 if (fw_table[i].type == AMD_BIOS_BIN) {
894 if (!fw_table[i].dest || !fw_table[i].size) {
895 printf("Error: BIOS binary destination and uncompressed size are required\n");
896 free(ctx->rom);
897 exit(1);
898 }
899 if (!fw_table[i].filename && !fw_table[i].src) {
900 printf("Error: BIOS binary assumed outside amdfw.rom but no source address given\n");
901 free(ctx->rom);
902 exit(1);
903 }
904 }
905
906 biosdir->entries[count].type = fw_table[i].type;
907 biosdir->entries[count].region_type = fw_table[i].region_type;
908 biosdir->entries[count].dest = fw_table[i].dest ?
909 fw_table[i].dest : (uint64_t)-1;
910 biosdir->entries[count].reset = fw_table[i].reset;
911 biosdir->entries[count].copy = fw_table[i].copy;
912 biosdir->entries[count].ro = fw_table[i].ro;
913 biosdir->entries[count].compressed = fw_table[i].zlib;
914 biosdir->entries[count].inst = fw_table[i].inst;
915 biosdir->entries[count].subprog = fw_table[i].subpr;
916
917 switch (fw_table[i].type) {
918 case AMD_BIOS_APOB:
919 biosdir->entries[count].size = fw_table[i].size;
920 biosdir->entries[count].source = fw_table[i].src;
921 break;
922 case AMD_BIOS_APOB_NV:
923 if (fw_table[i].src) {
924 /* If source is given, use that and its size */
925 biosdir->entries[count].source = fw_table[i].src;
926 biosdir->entries[count].size = fw_table[i].size;
927 } else {
928 /* Else reserve size bytes within amdfw.rom */
929 ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
930 biosdir->entries[count].source = RUN_CURRENT(*ctx);
931 biosdir->entries[count].size = ALIGN(
932 fw_table[i].size, ERASE_ALIGNMENT);
933 memset(BUFF_CURRENT(*ctx), 0xff,
934 biosdir->entries[count].size);
935 ctx->current = ctx->current
936 + biosdir->entries[count].size;
937 }
938 break;
939 case AMD_BIOS_BIN:
940 /* Don't make a 2nd copy, point to the same one */
941 if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2,
942 &biosdir->entries[count].source,
943 &biosdir->entries[count].size))
944 break;
945
946 /* level 2, or level 1 and no copy found in level 2 */
947 biosdir->entries[count].source = fw_table[i].src;
948 biosdir->entries[count].dest = fw_table[i].dest;
949 biosdir->entries[count].size = fw_table[i].size;
950
951 if (!fw_table[i].filename)
952 break;
953
954 bytes = copy_blob(BUFF_CURRENT(*ctx),
955 fw_table[i].filename, BUFF_ROOM(*ctx));
956 if (bytes <= 0) {
957 free(ctx->rom);
958 exit(1);
959 }
960
961 biosdir->entries[count].source = RUN_CURRENT(*ctx);
962
963 ctx->current = ALIGN(ctx->current + bytes, 0x100U);
964 break;
965 default: /* everything else is copied from input */
966 if (fw_table[i].type == AMD_BIOS_APCB ||
967 fw_table[i].type == AMD_BIOS_APCB_BK)
968 ctx->current = ALIGN(
969 ctx->current, ERASE_ALIGNMENT);
970
971 bytes = copy_blob(BUFF_CURRENT(*ctx),
972 fw_table[i].filename, BUFF_ROOM(*ctx));
973 if (bytes <= 0) {
974 free(ctx->rom);
975 exit(1);
976 }
977
978 biosdir->entries[count].size = (uint32_t)bytes;
979 biosdir->entries[count].source = RUN_CURRENT(*ctx);
980
981 ctx->current = ALIGN(ctx->current + bytes, 0x100U);
982 break;
983 }
984
985 count++;
986 }
987
988 if (biosdir2) {
989 biosdir->entries[count].type = AMD_BIOS_L2_PTR;
990 biosdir->entries[count].size =
991 + MAX_BIOS_ENTRIES
992 * sizeof(bios_directory_entry);
993 biosdir->entries[count].source =
994 BUFF_TO_RUN(*ctx, biosdir2);
995 biosdir->entries[count].subprog = 0;
996 biosdir->entries[count].inst = 0;
997 biosdir->entries[count].copy = 0;
998 biosdir->entries[count].compressed = 0;
999 biosdir->entries[count].dest = -1;
1000 biosdir->entries[count].reset = 0;
1001 biosdir->entries[count].ro = 0;
1002 count++;
1003 }
1004
1005 if (count > MAX_BIOS_ENTRIES) {
1006 printf("Error: BIOS entries exceeds max allowed items\n");
1007 free(ctx->rom);
1008 exit(1);
1009 }
1010
1011 fill_dir_header(biosdir, count, cookie);
1012}
Martin Rothd3ce8c82019-07-13 20:13:07 -06001013// Unused values: CDEPqR
1014static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:";
Marc Jones90099b62016-09-20 21:05:45 -06001015
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001016static struct option long_options[] = {
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001017 {"xhci", required_argument, 0, 'x' },
1018 {"imc", required_argument, 0, 'i' },
1019 {"gec", required_argument, 0, 'g' },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001020 /* PSP Directory Table items */
Marshall Dawson67d868d2019-02-28 11:43:40 -07001021 {"combo-capable", no_argument, 0, 'A' },
Marshall Dawson24f73d42019-04-01 10:48:43 -06001022 {"multilevel", no_argument, 0, 'M' },
Marshall Dawsondbae6322019-03-04 10:31:03 -07001023 {"subprogram", required_argument, 0, 'S' },
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001024 {"pubkey", required_argument, 0, 'p' },
1025 {"bootloader", required_argument, 0, 'b' },
1026 {"smufirmware", required_argument, 0, 's' },
1027 {"recovery", required_argument, 0, 'r' },
1028 {"rtmpubkey", required_argument, 0, 'k' },
1029 {"secureos", required_argument, 0, 'c' },
1030 {"nvram", required_argument, 0, 'n' },
1031 {"securedebug", required_argument, 0, 'd' },
1032 {"trustlets", required_argument, 0, 't' },
1033 {"trustletkey", required_argument, 0, 'u' },
1034 {"smufirmware2", required_argument, 0, 'w' },
1035 {"smuscs", required_argument, 0, 'm' },
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001036 {"soft-fuse", required_argument, 0, 'T' },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001037 {"abl-image", required_argument, 0, 'z' },
1038 {"sec-gasket", required_argument, 0, 'J' },
1039 {"mp2-fw", required_argument, 0, 'B' },
1040 {"drv-entry-pts", required_argument, 0, 'K' },
1041 {"ikek", required_argument, 0, 'L' },
1042 {"s0i3drv", required_argument, 0, 'Y' },
1043 {"secdebug", required_argument, 0, 'N' },
1044 {"token-unlock", no_argument, 0, 'U' },
1045 {"whitelist", required_argument, 0, 'W' },
Martin Rothd3ce8c82019-07-13 20:13:07 -06001046 {"verstage", required_argument, 0, 'Z' },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001047 /* BIOS Directory Table items */
1048 {"instance", required_argument, 0, 'I' },
1049 {"apcb", required_argument, 0, 'a' },
1050 {"apob-base", required_argument, 0, 'Q' },
1051 {"bios-bin", required_argument, 0, 'V' },
1052 {"bios-bin-src", required_argument, 0, 'e' },
1053 {"bios-bin-dest", required_argument, 0, 'v' },
1054 {"bios-uncomp-size", required_argument, 0, 'j' },
1055 {"pmu-inst", required_argument, 0, 'y' },
1056 {"pmu-data", required_argument, 0, 'G' },
1057 {"ucode", required_argument, 0, 'O' },
1058 {"mp2-config", required_argument, 0, 'X' },
1059 {"apob-nv-base", required_argument, 0, 'F' },
1060 {"apob-nv-size", required_argument, 0, 'H' },
1061 /* other */
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001062 {"output", required_argument, 0, 'o' },
1063 {"flashsize", required_argument, 0, 'f' },
Martin Roth0d3b1182017-10-03 14:16:04 -06001064 {"location", required_argument, 0, 'l' },
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001065 {"help", no_argument, 0, 'h' },
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001066 {NULL, 0, 0, 0 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001067};
1068
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001069static void register_fw_fuse(char *str)
1070{
1071 int i;
1072
1073 for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
1074 if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN)
1075 continue;
1076
1077 amd_psp_fw_table[i].other = strtoull(str, NULL, 16);
1078 return;
1079 }
1080}
1081
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001082static void register_fw_token_unlock(void)
1083{
1084 int i;
1085
1086 for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
1087 if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK)
1088 continue;
1089
1090 amd_psp_fw_table[i].other = 1;
1091 return;
1092 }
1093}
1094
Marshall Dawsondbae6322019-03-04 10:31:03 -07001095static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[])
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001096{
Martin Roth8806f7f2016-11-08 10:44:18 -07001097 unsigned int i;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001098
Martin Rothcd15bc82016-11-08 11:34:02 -07001099 for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) {
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001100 if (amd_fw_table[i].type == type) {
1101 amd_fw_table[i].filename = filename;
1102 return;
1103 }
1104 }
1105
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001106 for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
Marshall Dawsondbae6322019-03-04 10:31:03 -07001107 if (amd_psp_fw_table[i].type != type)
1108 continue;
1109
1110 if (amd_psp_fw_table[i].subprog == sub) {
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001111 amd_psp_fw_table[i].filename = filename;
1112 return;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001113 }
1114 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001115}
1116
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001117static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[])
1118{
1119 int i;
1120
1121 for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) {
1122 if (amd_bios_table[i].type == type
1123 && amd_bios_table[i].inst == ins
1124 && amd_bios_table[i].subpr == sub) {
1125 amd_bios_table[i].filename = name;
1126 return;
1127 }
1128 }
1129}
1130
Martin Rothec933132019-07-13 20:03:34 -06001131static void register_fw_addr(amd_bios_type type, char *src_str,
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001132 char *dst_str, char *size_str)
1133{
1134 int i;
1135 for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) {
1136 if (amd_bios_table[i].type != type)
1137 continue;
1138
1139 if (src_str)
1140 amd_bios_table[i].src = strtoull(src_str, NULL, 16);
1141 if (dst_str)
1142 amd_bios_table[i].dest = strtoull(dst_str, NULL, 16);
1143 if (size_str)
1144 amd_bios_table[i].size = strtoul(size_str, NULL, 16);
1145
1146 return;
1147 }
1148}
1149
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001150int main(int argc, char **argv)
1151{
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001152 int c;
Martin Roth31d95a22016-11-08 11:22:12 -07001153 int retval = 0;
Martin Roth60f15512016-11-08 09:55:01 -07001154 char *tmp;
Martin Roth8806f7f2016-11-08 10:44:18 -07001155 char *rom = NULL;
Marshall Dawson239286c2019-02-23 16:42:46 -07001156 embedded_firmware *amd_romsig;
1157 psp_directory_table *pspdir;
Marshall Dawson67d868d2019-02-28 11:43:40 -07001158 int comboable = 0;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001159 int fuse_defined = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001160 int targetfd;
Martin Roth8806f7f2016-11-08 10:44:18 -07001161 char *output = NULL;
Marshall Dawson2794a862019-03-04 16:53:15 -07001162 context ctx = {
1163 .rom_size = CONFIG_ROM_SIZE,
1164 };
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001165 /* Values cleared after each firmware or parameter, regardless if N/A */
1166 uint8_t sub = 0, instance = 0;
1167 int abl_image = 0;
Martin Roth0d3b1182017-10-03 14:16:04 -06001168 uint32_t dir_location = 0;
1169 uint32_t romsig_offset;
Martin Roth60f15512016-11-08 09:55:01 -07001170 uint32_t rom_base_address;
Marshall Dawson24f73d42019-04-01 10:48:43 -06001171 int multi = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001172
1173 while (1) {
1174 int optindex = 0;
1175
1176 c = getopt_long(argc, argv, optstring, long_options, &optindex);
1177
1178 if (c == -1)
1179 break;
1180
1181 switch (c) {
1182 case 'x':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001183 register_fw_filename(AMD_FW_XHCI, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001184 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001185 break;
1186 case 'i':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001187 register_fw_filename(AMD_FW_IMC, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001188 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001189 break;
1190 case 'g':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001191 register_fw_filename(AMD_FW_GEC, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001192 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001193 break;
Marshall Dawson67d868d2019-02-28 11:43:40 -07001194 case 'A':
1195 comboable = 1;
1196 break;
Marshall Dawson24f73d42019-04-01 10:48:43 -06001197 case 'M':
1198 multi = 1;
1199 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001200 case 'U':
1201 register_fw_token_unlock();
1202 sub = instance = 0;
1203 break;
Marshall Dawsondbae6322019-03-04 10:31:03 -07001204 case 'S':
1205 sub = (uint8_t)strtoul(optarg, &tmp, 16);
1206 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001207 case 'I':
1208 instance = strtoul(optarg, &tmp, 16);
1209 break;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001210 case 'p':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001211 register_fw_filename(AMD_FW_PSP_PUBKEY, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001212 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001213 break;
1214 case 'b':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001215 register_fw_filename(AMD_FW_PSP_BOOTLOADER,
1216 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001217 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001218 break;
1219 case 's':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001220 register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE,
1221 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001222 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001223 break;
1224 case 'r':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001225 register_fw_filename(AMD_FW_PSP_RECOVERY, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001226 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001227 break;
1228 case 'k':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001229 register_fw_filename(AMD_FW_PSP_RTM_PUBKEY,
1230 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001231 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001232 break;
1233 case 'c':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001234 register_fw_filename(AMD_FW_PSP_SECURED_OS,
1235 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001236 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001237 break;
1238 case 'n':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001239 register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001240 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001241 break;
1242 case 'd':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001243 register_fw_filename(AMD_FW_PSP_SECURED_DEBUG,
1244 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001245 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001246 break;
1247 case 't':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001248 register_fw_filename(AMD_FW_PSP_TRUSTLETS, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001249 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001250 break;
1251 case 'u':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001252 register_fw_filename(AMD_FW_PSP_TRUSTLETKEY,
1253 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001254 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001255 break;
1256 case 'w':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001257 register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2,
1258 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001259 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001260 break;
1261 case 'm':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001262 register_fw_filename(AMD_FW_PSP_SMUSCS, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001263 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001264 break;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001265 case 'T':
1266 register_fw_fuse(optarg);
1267 fuse_defined = 1;
1268 sub = 0;
1269 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001270 case 'a':
1271 register_bdt_data(AMD_BIOS_APCB, sub, instance, optarg);
1272 register_bdt_data(AMD_BIOS_APCB_BK, sub,
1273 instance, optarg);
1274 sub = instance = 0;
1275 break;
1276 case 'Q':
1277 /* APOB destination */
1278 register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0);
1279 sub = instance = 0;
1280 break;
1281 case 'F':
1282 /* APOB NV source */
1283 register_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0);
1284 sub = instance = 0;
1285 break;
1286 case 'H':
1287 /* APOB NV size */
1288 register_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg);
1289 sub = instance = 0;
1290 break;
1291 case 'V':
1292 register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg);
1293 sub = instance = 0;
1294 break;
1295 case 'e':
1296 /* BIOS source */
1297 register_fw_addr(AMD_BIOS_BIN, optarg, 0, 0);
1298 sub = instance = 0;
1299 break;
1300 case 'v':
1301 /* BIOS destination */
1302 register_fw_addr(AMD_BIOS_BIN, 0, optarg, 0);
1303 sub = instance = 0;
1304 break;
1305 case 'j':
1306 /* BIOS destination size */
1307 register_fw_addr(AMD_BIOS_BIN, 0, 0, optarg);
1308 sub = instance = 0;
1309 break;
1310 case 'y':
1311 register_bdt_data(AMD_BIOS_PMUI, sub, instance, optarg);
1312 sub = instance = 0;
1313 break;
1314 case 'G':
1315 register_bdt_data(AMD_BIOS_PMUD, sub, instance, optarg);
1316 sub = instance = 0;
1317 break;
1318 case 'O':
1319 register_bdt_data(AMD_BIOS_UCODE, sub,
1320 instance, optarg);
1321 sub = instance = 0;
1322 break;
1323 case 'J':
1324 register_fw_filename(AMD_SEC_GASKET, sub, optarg);
1325 sub = instance = 0;
1326 break;
1327 case 'B':
1328 register_fw_filename(AMD_MP2_FW, sub, optarg);
1329 sub = instance = 0;
1330 break;
1331 case 'z':
1332 register_fw_filename(AMD_ABL0 + abl_image++,
1333 sub, optarg);
1334 sub = instance = 0;
1335 break;
1336 case 'X':
1337 register_bdt_data(AMD_BIOS_MP2_CFG, sub,
1338 instance, optarg);
1339 sub = instance = 0;
1340 break;
1341 case 'K':
1342 register_fw_filename(AMD_DRIVER_ENTRIES, sub, optarg);
1343 sub = instance = 0;
1344 break;
1345 case 'L':
1346 register_fw_filename(AMD_WRAPPED_IKEK, sub, optarg);
1347 sub = instance = 0;
1348 break;
1349 case 'Y':
1350 register_fw_filename(AMD_S0I3_DRIVER, sub, optarg);
1351 sub = instance = 0;
1352 break;
1353 case 'N':
1354 register_fw_filename(AMD_DEBUG_UNLOCK, sub, optarg);
1355 sub = instance = 0;
1356 break;
1357 case 'W':
1358 register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg);
1359 sub = instance = 0;
1360 break;
Martin Rothd3ce8c82019-07-13 20:13:07 -06001361 case 'Z':
1362 register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg);
1363 sub = instance = 0;
1364 break;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001365 case 'o':
1366 output = optarg;
1367 break;
Martin Roth60f15512016-11-08 09:55:01 -07001368 case 'f':
Marshall Dawson2794a862019-03-04 16:53:15 -07001369 ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16);
Martin Roth60f15512016-11-08 09:55:01 -07001370 if (*tmp != '\0') {
1371 printf("Error: ROM size specified"
1372 " incorrectly (%s)\n\n", optarg);
Martin Roth31d95a22016-11-08 11:22:12 -07001373 retval = 1;
Martin Roth60f15512016-11-08 09:55:01 -07001374 }
1375 break;
Martin Roth0d3b1182017-10-03 14:16:04 -06001376 case 'l':
1377 dir_location = (uint32_t)strtoul(optarg, &tmp, 16);
1378 if (*tmp != '\0') {
1379 printf("Error: Directory Location specified"
1380 " incorrectly (%s)\n\n", optarg);
1381 retval = 1;
1382 }
1383 break;
1384
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001385 case 'h':
1386 usage();
Martin Roth31d95a22016-11-08 11:22:12 -07001387 return 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001388 default:
1389 break;
1390 }
1391 }
1392
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001393 if (!fuse_defined)
1394 register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN);
1395
Martin Roth8806f7f2016-11-08 10:44:18 -07001396 if (!output) {
Martin Roth31d95a22016-11-08 11:22:12 -07001397 printf("Error: Output value is not specified.\n\n");
1398 retval = 1;
1399 }
1400
Marshall Dawson2794a862019-03-04 16:53:15 -07001401 if (ctx.rom_size % 1024 != 0) {
Martin Roth60f15512016-11-08 09:55:01 -07001402 printf("Error: ROM Size (%d bytes) should be a multiple of"
Marshall Dawson2794a862019-03-04 16:53:15 -07001403 " 1024 bytes.\n\n", ctx.rom_size);
Martin Roth31d95a22016-11-08 11:22:12 -07001404 retval = 1;
Martin Roth60f15512016-11-08 09:55:01 -07001405 }
1406
Marshall Dawson2794a862019-03-04 16:53:15 -07001407 if (ctx.rom_size < MIN_ROM_KB * 1024) {
Martin Roth31d95a22016-11-08 11:22:12 -07001408 printf("Error: ROM Size (%dKB) must be at least %dKB.\n\n",
Marshall Dawson2794a862019-03-04 16:53:15 -07001409 ctx.rom_size / 1024, MIN_ROM_KB);
Martin Roth31d95a22016-11-08 11:22:12 -07001410 retval = 1;
1411 }
1412
1413 if (retval) {
1414 usage();
1415 return retval;
Martin Roth60f15512016-11-08 09:55:01 -07001416 }
1417
Marshall Dawson2794a862019-03-04 16:53:15 -07001418 printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024);
Martin Roth60f15512016-11-08 09:55:01 -07001419
Marshall Dawson2794a862019-03-04 16:53:15 -07001420 rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1;
Martin Roth0d3b1182017-10-03 14:16:04 -06001421 if (dir_location && (dir_location < rom_base_address)) {
1422 printf("Error: Directory location outside of ROM.\n\n");
1423 return 1;
1424 }
1425
1426 switch (dir_location) {
1427 case 0: /* Fall through */
1428 case 0xFFFA0000: /* Fall through */
1429 case 0xFFF20000: /* Fall through */
1430 case 0xFFE20000: /* Fall through */
1431 case 0xFFC20000: /* Fall through */
1432 case 0xFF820000: /* Fall through */
1433 case 0xFF020000: /* Fall through */
1434 break;
1435 default:
1436 printf("Error: Invalid Directory location.\n");
1437 printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n");
1438 printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n");
1439 return 1;
1440 }
1441
Marshall Dawson2794a862019-03-04 16:53:15 -07001442 ctx.rom = malloc(ctx.rom_size);
1443 if (!ctx.rom) {
1444 printf("Error: Failed to allocate memory\n");
Martin Roth31d95a22016-11-08 11:22:12 -07001445 return 1;
Marshall Dawson2794a862019-03-04 16:53:15 -07001446 }
1447 memset(ctx.rom, 0xFF, ctx.rom_size);
Martin Roth60f15512016-11-08 09:55:01 -07001448
Martin Roth0d3b1182017-10-03 14:16:04 -06001449 if (dir_location)
Marshall Dawson2794a862019-03-04 16:53:15 -07001450 romsig_offset = ctx.current = dir_location - rom_base_address;
Martin Roth0d3b1182017-10-03 14:16:04 -06001451 else
Marshall Dawson2794a862019-03-04 16:53:15 -07001452 romsig_offset = ctx.current = AMD_ROMSIG_OFFSET;
1453 printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n",
1454 RUN_CURRENT(ctx));
Martin Roth0d3b1182017-10-03 14:16:04 -06001455
Marshall Dawson2794a862019-03-04 16:53:15 -07001456 amd_romsig = BUFF_OFFSET(ctx, romsig_offset);
Marshall Dawson239286c2019-02-23 16:42:46 -07001457 amd_romsig->signature = EMBEDDED_FW_SIGNATURE;
1458 amd_romsig->imc_entry = 0;
1459 amd_romsig->gec_entry = 0;
1460 amd_romsig->xhci_entry = 0;
Martin Roth60f15512016-11-08 09:55:01 -07001461
Marshall Dawson2794a862019-03-04 16:53:15 -07001462 integrate_firmwares(&ctx, amd_romsig, amd_fw_table);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001463
Patrick Georgi900a2542020-02-17 16:52:40 +01001464 ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */
Marshall Dawson2794a862019-03-04 16:53:15 -07001465
Marshall Dawson24f73d42019-04-01 10:48:43 -06001466 if (multi) {
1467 /* Do 2nd PSP directory followed by 1st */
1468 psp_directory_table *pspdir2 = new_psp_dir(&ctx, multi);
1469 integrate_psp_firmwares(&ctx, pspdir2, 0,
1470 amd_psp_fw_table, PSPL2_COOKIE);
1471
1472 pspdir = new_psp_dir(&ctx, multi);
1473 integrate_psp_firmwares(&ctx, pspdir, pspdir2,
1474 amd_psp_fw_table, PSP_COOKIE);
1475 } else {
1476 /* flat: PSP 1 cookie and no pointer to 2nd table */
1477 pspdir = new_psp_dir(&ctx, multi);
1478 integrate_psp_firmwares(&ctx, pspdir, 0,
1479 amd_psp_fw_table, PSP_COOKIE);
1480 }
Marshall Dawson2794a862019-03-04 16:53:15 -07001481
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001482 if (comboable)
Marshall Dawson2794a862019-03-04 16:53:15 -07001483 amd_romsig->comboable = BUFF_TO_RUN(ctx, pspdir);
Marshall Dawson67d868d2019-02-28 11:43:40 -07001484 else
Marshall Dawson2794a862019-03-04 16:53:15 -07001485 amd_romsig->psp_entry = BUFF_TO_RUN(ctx, pspdir);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001486
zbaoc3a08a92016-03-02 14:47:27 +08001487#if PSP_COMBO
Marshall Dawson2794a862019-03-04 16:53:15 -07001488 psp_combo_directory *combo_dir = new_combo_dir(&ctx);
1489 amd_romsig->comboable = BUFF_TO_RUN(ctx, combo_dir);
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001490 /* 0 -Compare PSP ID, 1 -Compare chip family ID */
1491 combo_dir->entries[0].id_sel = 0;
1492 /* TODO: PSP ID. Documentation is needed. */
1493 combo_dir->entries[0].id = 0x10220B00;
Marshall Dawson2794a862019-03-04 16:53:15 -07001494 combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir);
Zheng Bao4fcc9f22015-11-20 12:29:04 +08001495
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001496 combo_dir->header.lookup = 1;
Marshall Dawsona378c222019-03-04 16:52:07 -07001497 fill_dir_header(combo_dir, 1, PSP2_COOKIE);
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001498#endif
Zheng Bao4fcc9f22015-11-20 12:29:04 +08001499
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001500 if (have_bios_tables(amd_bios_table)) {
1501 bios_directory_table *biosdir;
1502 if (multi) {
1503 /* Do 2nd level BIOS directory followed by 1st */
1504 bios_directory_table *biosdir2 =
1505 new_bios_dir(&ctx, multi);
1506 integrate_bios_firmwares(&ctx, biosdir2, 0,
1507 amd_bios_table, BDT2_COOKIE);
1508
1509 biosdir = new_bios_dir(&ctx, multi);
1510 integrate_bios_firmwares(&ctx, biosdir, biosdir2,
1511 amd_bios_table, BDT1_COOKIE);
1512 } else {
1513 /* flat: BDT1 cookie and no pointer to 2nd table */
1514 biosdir = new_bios_dir(&ctx, multi);
1515 integrate_bios_firmwares(&ctx, biosdir, 0,
1516 amd_bios_table, BDT1_COOKIE);
1517 }
1518 amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir);
1519 }
1520
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001521 targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666);
Martin Roth31d95a22016-11-08 11:22:12 -07001522 if (targetfd >= 0) {
Marshall Dawson2794a862019-03-04 16:53:15 -07001523 write(targetfd, amd_romsig, ctx.current - romsig_offset);
Martin Roth31d95a22016-11-08 11:22:12 -07001524 close(targetfd);
1525 } else {
1526 printf("Error: could not open file: %s\n", output);
1527 retval = 1;
1528 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001529
Martin Roth31d95a22016-11-08 11:22:12 -07001530 free(rom);
1531 return retval;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001532}