Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <arch/smp/mpspec.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <string.h> |
| 25 | #include <stdint.h> |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 26 | #include <cpu/amd/amdfam10_sysconf.h> |
| 27 | |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 28 | extern u8 bus_rs780[11]; |
| 29 | extern u8 bus_sb700[2]; |
| 30 | |
| 31 | extern u32 apicid_sb700; |
| 32 | |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 33 | extern u32 sbdn_rs780; |
| 34 | extern u32 sbdn_sb700; |
| 35 | |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 36 | static void *smp_write_config_table(void *v) |
| 37 | { |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 38 | struct mp_config_table *mc; |
Patrick Georgi | 8cda969 | 2010-11-21 14:40:09 +0000 | [diff] [blame^] | 39 | int bus_isa; |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 40 | |
| 41 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 42 | |
Uwe Hermann | 55dc223 | 2010-10-25 15:32:07 +0000 | [diff] [blame] | 43 | mptable_init(mc, "M4A785-M ", LAPIC_ADDR); |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 44 | |
| 45 | smp_write_processors(mc); |
| 46 | |
| 47 | get_bus_conf(); |
| 48 | |
Patrick Georgi | 8cda969 | 2010-11-21 14:40:09 +0000 | [diff] [blame^] | 49 | mptable_write_buses(mc, NULL, &bus_isa); |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 50 | |
| 51 | /* I/O APICs: APIC ID Version State Address */ |
| 52 | { |
| 53 | device_t dev; |
| 54 | u32 dword; |
| 55 | u8 byte; |
| 56 | |
| 57 | dev = |
| 58 | dev_find_slot(bus_sb700[0], |
| 59 | PCI_DEVFN(sbdn_sb700 + 0x14, 0)); |
| 60 | if (dev) { |
| 61 | dword = pci_read_config32(dev, 0x74) & 0xfffffff0; |
| 62 | smp_write_ioapic(mc, apicid_sb700, 0x11, dword); |
| 63 | |
| 64 | /* Initialize interrupt mapping */ |
| 65 | /* aza */ |
| 66 | byte = pci_read_config8(dev, 0x63); |
| 67 | byte &= 0xf8; |
| 68 | byte |= 0; /* 0: INTA, ...., 7: INTH */ |
| 69 | pci_write_config8(dev, 0x63, byte); |
| 70 | |
| 71 | /* SATA */ |
| 72 | dword = pci_read_config32(dev, 0xac); |
| 73 | dword &= ~(7 << 26); |
| 74 | dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ |
| 75 | /* dword |= 1<<22; PIC and APIC co exists */ |
| 76 | pci_write_config32(dev, 0xac, dword); |
| 77 | |
| 78 | /* |
| 79 | * 00:12.0: PROG SATA : INT F |
| 80 | * 00:13.0: INTA USB_0 |
| 81 | * 00:13.1: INTB USB_1 |
| 82 | * 00:13.2: INTC USB_2 |
| 83 | * 00:13.3: INTD USB_3 |
| 84 | * 00:13.4: INTC USB_4 |
| 85 | * 00:13.5: INTD USB2 |
| 86 | * 00:14.1: INTA IDE |
| 87 | * 00:14.2: Prog HDA : INT E |
| 88 | * 00:14.5: INTB ACI |
| 89 | * 00:14.6: INTB MCI |
| 90 | */ |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 95 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
Tobias Diedrich | b907d32 | 2010-10-26 22:40:16 +0000 | [diff] [blame] | 96 | smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
Juhana Helovuo | d09d1f7 | 2010-09-13 14:51:26 +0000 | [diff] [blame] | 97 | |
| 98 | mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); |
| 99 | |
| 100 | /* PCI interrupts are level triggered, and are |
| 101 | * associated with a specific bus/device/function tuple. |
| 102 | */ |
| 103 | #if CONFIG_GENERATE_ACPI_TABLES == 0 |
| 104 | #define PCI_INT(bus, dev, fn, pin) \ |
| 105 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) |
| 106 | #else |
| 107 | #define PCI_INT(bus, dev, fn, pin) |
| 108 | #endif |
| 109 | |
| 110 | /* usb */ |
| 111 | PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ |
| 112 | PCI_INT(0x0, 0x12, 0x1, 0x11); |
| 113 | PCI_INT(0x0, 0x13, 0x0, 0x12); |
| 114 | PCI_INT(0x0, 0x13, 0x1, 0x13); |
| 115 | PCI_INT(0x0, 0x14, 0x0, 0x10); |
| 116 | |
| 117 | /* sata */ |
| 118 | PCI_INT(0x0, 0x11, 0x0, 0x16); |
| 119 | |
| 120 | /* HD Audio: b0:d20:f1:reg63 should be 0. */ |
| 121 | /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ |
| 122 | |
| 123 | /* on board NIC & Slot PCIE. */ |
| 124 | /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ |
| 125 | /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ |
| 126 | PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ |
| 127 | /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ |
| 128 | PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); |
| 129 | /* configuration B doesnt need dev 5,6,7 */ |
| 130 | /* |
| 131 | * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); |
| 132 | * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); |
| 133 | * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); |
| 134 | */ |
| 135 | PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); |
| 136 | PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ |
| 137 | |
| 138 | /* PCI slots */ |
| 139 | /* PCI_SLOT 0. */ |
| 140 | PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); |
| 141 | PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); |
| 142 | PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); |
| 143 | PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); |
| 144 | |
| 145 | /* PCI_SLOT 1. */ |
| 146 | PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); |
| 147 | PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); |
| 148 | PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); |
| 149 | PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); |
| 150 | |
| 151 | /* PCI_SLOT 2. */ |
| 152 | PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); |
| 153 | PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); |
| 154 | PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); |
| 155 | PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); |
| 156 | |
| 157 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 158 | IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); |
| 159 | IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); |
| 160 | /* There is no extension information... */ |
| 161 | |
| 162 | /* Compute the checksums */ |
| 163 | mc->mpe_checksum = |
| 164 | smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
| 165 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 166 | printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", |
| 167 | mc, smp_next_mpe_entry(mc)); |
| 168 | return smp_next_mpe_entry(mc); |
| 169 | } |
| 170 | |
| 171 | unsigned long write_smp_table(unsigned long addr) |
| 172 | { |
| 173 | void *v; |
| 174 | v = smp_write_floating_table(addr); |
| 175 | return (unsigned long)smp_write_config_table(v); |
| 176 | } |