Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
Stefan Reinauer | 5605f1b | 2013-03-21 18:43:51 -0700 | [diff] [blame] | 7 | #include <device/pci_def.h> |
Angel Pons | 2178b72 | 2020-05-31 00:55:35 +0200 | [diff] [blame] | 8 | #include "iobp.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include "pch.h" |
| 10 | |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 11 | #ifdef __SIMPLE_DEVICE__ |
| 12 | static pci_devfn_t pch_get_lpc_device(void) |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 13 | { |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 14 | return PCI_DEV(0, 0x1f, 0); |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 15 | } |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 16 | #else |
| 17 | static struct device *pch_get_lpc_device(void) |
| 18 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 19 | return pcidev_on_root(0x1f, 0); |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 20 | } |
| 21 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 22 | |
| 23 | int pch_silicon_revision(void) |
| 24 | { |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 25 | static int pch_revision_id = -1; |
| 26 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | if (pch_revision_id < 0) |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 28 | pch_revision_id = pci_read_config8(pch_get_lpc_device(), |
| 29 | PCI_REVISION_ID); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | return pch_revision_id; |
| 31 | } |
| 32 | |
Tristan Corrick | d3f01b2 | 2018-12-06 22:46:58 +1300 | [diff] [blame] | 33 | int pch_silicon_id(void) |
| 34 | { |
| 35 | static int pch_id = -1; |
| 36 | |
| 37 | if (pch_id < 0) |
| 38 | pch_id = pci_read_config16(pch_get_lpc_device(), PCI_DEVICE_ID); |
| 39 | |
| 40 | return pch_id; |
| 41 | } |
| 42 | |
Angel Pons | 3173993 | 2020-07-03 23:14:40 +0200 | [diff] [blame] | 43 | enum pch_platform_type get_pch_platform_type(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 44 | { |
Angel Pons | 3173993 | 2020-07-03 23:14:40 +0200 | [diff] [blame] | 45 | const u16 did = pci_read_config16(pch_get_lpc_device(), PCI_DEVICE_ID); |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 46 | |
Angel Pons | 3173993 | 2020-07-03 23:14:40 +0200 | [diff] [blame] | 47 | /* Check if this is a LPT-LP or WPT-LP device ID */ |
| 48 | if ((did & 0xff00) == 0x9c00) |
| 49 | return PCH_TYPE_ULT; |
| 50 | |
| 51 | /* Non-LP laptop SKUs have an odd device ID (least significant bit is one) */ |
| 52 | if (did & 1) |
| 53 | return PCH_TYPE_MOBILE; |
| 54 | |
| 55 | /* Desktop and Server SKUs have an even device ID */ |
| 56 | return PCH_TYPE_DESKTOP; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 57 | } |
| 58 | |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 59 | u16 get_pmbase(void) |
| 60 | { |
| 61 | static u16 pmbase; |
| 62 | |
| 63 | if (!pmbase) |
| 64 | pmbase = pci_read_config16(pch_get_lpc_device(), |
| 65 | PMBASE) & 0xfffc; |
| 66 | return pmbase; |
| 67 | } |
| 68 | |
| 69 | u16 get_gpiobase(void) |
| 70 | { |
| 71 | static u16 gpiobase; |
| 72 | |
| 73 | if (!gpiobase) |
| 74 | gpiobase = pci_read_config16(pch_get_lpc_device(), |
| 75 | GPIOBASE) & 0xfffc; |
| 76 | return gpiobase; |
| 77 | } |
| 78 | |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 79 | #ifndef __SIMPLE_DEVICE__ |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 80 | |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 81 | /* Put device in D3Hot Power State */ |
Elyes HAOUAS | 38f1d13 | 2018-09-17 08:44:18 +0200 | [diff] [blame] | 82 | static void pch_enable_d3hot(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 83 | { |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 84 | pci_or_config32(dev, PCH_PCS, PCH_PCS_PS_D3HOT); |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 85 | } |
| 86 | |
Frans Hendriks | e6bf51f | 2019-05-01 10:48:31 +0200 | [diff] [blame] | 87 | /* Set bit in function disable register to hide this device */ |
Elyes HAOUAS | 38f1d13 | 2018-09-17 08:44:18 +0200 | [diff] [blame] | 88 | void pch_disable_devfn(struct device *dev) |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 89 | { |
| 90 | switch (dev->path.pci.devfn) { |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 91 | case PCI_DEVFN(19, 0): /* Audio DSP */ |
| 92 | RCBA32_OR(FD, PCH_DISABLE_ADSPD); |
| 93 | break; |
| 94 | case PCI_DEVFN(20, 0): /* XHCI */ |
| 95 | RCBA32_OR(FD, PCH_DISABLE_XHCI); |
| 96 | break; |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 97 | case PCI_DEVFN(21, 0): /* DMA */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 98 | pch_enable_d3hot(dev); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 99 | pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0, SIO_IOBP_FUNCDIS_DIS); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 100 | break; |
| 101 | case PCI_DEVFN(21, 1): /* I2C0 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 102 | pch_enable_d3hot(dev); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 103 | pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0, SIO_IOBP_FUNCDIS_DIS); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 104 | break; |
| 105 | case PCI_DEVFN(21, 2): /* I2C1 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 106 | pch_enable_d3hot(dev); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 107 | pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0, SIO_IOBP_FUNCDIS_DIS); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 108 | break; |
| 109 | case PCI_DEVFN(21, 3): /* SPI0 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 110 | pch_enable_d3hot(dev); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 111 | pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0, SIO_IOBP_FUNCDIS_DIS); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 112 | break; |
| 113 | case PCI_DEVFN(21, 4): /* SPI1 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 114 | pch_enable_d3hot(dev); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 115 | pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0, SIO_IOBP_FUNCDIS_DIS); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 116 | break; |
| 117 | case PCI_DEVFN(21, 5): /* UART0 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 118 | pch_enable_d3hot(dev); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 119 | pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0, SIO_IOBP_FUNCDIS_DIS); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 120 | break; |
| 121 | case PCI_DEVFN(21, 6): /* UART1 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 122 | pch_enable_d3hot(dev); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 123 | pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0, SIO_IOBP_FUNCDIS_DIS); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 124 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 125 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 126 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 127 | break; |
| 128 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 129 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 130 | break; |
| 131 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 132 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 133 | break; |
| 134 | case PCI_DEVFN(22, 3): /* KT */ |
| 135 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 136 | break; |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 137 | case PCI_DEVFN(23, 0): /* SDIO */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 138 | pch_enable_d3hot(dev); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 139 | pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0, SIO_IOBP_FUNCDIS_DIS); |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 140 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
| 142 | RCBA32_OR(BUC, PCH_DISABLE_GBE); |
| 143 | break; |
| 144 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 145 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 146 | break; |
| 147 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 148 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 149 | break; |
| 150 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 151 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 152 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 153 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 154 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 155 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 156 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 157 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 158 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 159 | break; |
| 160 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 161 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 162 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 163 | case PCI_DEVFN(31, 0): /* LPC */ |
| 164 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 165 | break; |
| 166 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 167 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 168 | break; |
| 169 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 170 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 171 | break; |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 172 | case PCI_DEVFN(31, 5): /* SATA #2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 173 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 174 | break; |
| 175 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 176 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 177 | break; |
| 178 | } |
| 179 | } |
| 180 | |
Elyes HAOUAS | 38f1d13 | 2018-09-17 08:44:18 +0200 | [diff] [blame] | 181 | void pch_enable(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 182 | { |
Aaron Durbin | c0254e6 | 2013-06-20 01:20:30 -0500 | [diff] [blame] | 183 | /* PCH PCIe Root Ports are handled in PCIe driver. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 184 | if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) |
Aaron Durbin | c0254e6 | 2013-06-20 01:20:30 -0500 | [diff] [blame] | 185 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 186 | |
| 187 | if (!dev->enabled) { |
| 188 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 189 | |
| 190 | /* Ensure memory, io, and bus master are all disabled */ |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 191 | pci_and_config16(dev, PCI_COMMAND, |
| 192 | ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 193 | |
Aaron Durbin | 3fcd356 | 2013-06-19 13:20:37 -0500 | [diff] [blame] | 194 | /* Disable this device if possible */ |
| 195 | pch_disable_devfn(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 196 | } else { |
| 197 | /* Enable SERR */ |
Elyes HAOUAS | 73ae076 | 2020-04-28 10:13:05 +0200 | [diff] [blame] | 198 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 199 | } |
| 200 | } |
| 201 | |
| 202 | struct chip_operations southbridge_intel_lynxpoint_ops = { |
| 203 | CHIP_NAME("Intel Series 8 (Lynx Point) Southbridge") |
| 204 | .enable_dev = pch_enable, |
| 205 | }; |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 206 | |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 207 | #endif /* __SIMPLE_DEVICE__ */ |