Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
Kyösti Mälkki | ef84401 | 2013-06-25 23:17:43 +0300 | [diff] [blame] | 17 | // Use simple device model for this file even in ramstage |
| 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 20 | #include <stdint.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 21 | #include <arch/cpu.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 22 | #include <arch/io.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 23 | #include <device/pci_def.h> |
| 24 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 25 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 26 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | dcb688e | 2013-09-04 01:11:16 +0300 | [diff] [blame] | 27 | #include <cbmem.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 28 | #include <program_loading.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 29 | #include "gm45.h" |
| 30 | |
Arthur Heymans | eeaf9e4 | 2016-11-12 20:13:07 +0100 | [diff] [blame] | 31 | /* |
| 32 | * Decodes used Graphics Mode Select (GMS) to kilobytes. |
| 33 | * The options for 1M, 4M, 8M and 16M preallocated igd memory are |
| 34 | * undocumented but are verified to work. |
| 35 | */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 36 | u32 decode_igd_memory_size(const u32 gms) |
| 37 | { |
Arthur Heymans | eeaf9e4 | 2016-11-12 20:13:07 +0100 | [diff] [blame] | 38 | static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, |
| 39 | 96, 160, 224, 352 }; |
| 40 | |
| 41 | if (gms > ARRAY_SIZE(ggc2uma)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 42 | die("Bad Graphics Mode Select (GMS) setting.\n"); |
Arthur Heymans | eeaf9e4 | 2016-11-12 20:13:07 +0100 | [diff] [blame] | 43 | |
| 44 | return ggc2uma[gms] << 10; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 45 | } |
| 46 | |
| 47 | /** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ |
| 48 | u32 decode_igd_gtt_size(const u32 gsm) |
| 49 | { |
| 50 | switch (gsm) { |
| 51 | case 0: |
| 52 | return 0 << 10; |
| 53 | case 1: |
| 54 | return 1 << 10; |
| 55 | case 3: |
| 56 | case 9: |
| 57 | return 2 << 10; |
| 58 | case 10: |
| 59 | return 3 << 10; |
| 60 | case 11: |
| 61 | return 4 << 10; |
| 62 | default: |
| 63 | die("Bad Graphics Stolen Memory (GSM) setting.\n"); |
| 64 | return 0; |
| 65 | } |
| 66 | } |
| 67 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 68 | static uintptr_t smm_region_start(void) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 69 | { |
Kyösti Mälkki | 3f9a62e | 2013-06-20 20:25:21 +0300 | [diff] [blame] | 70 | const pci_devfn_t dev = PCI_DEV(0, 0, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 71 | |
| 72 | u32 tor; |
| 73 | |
| 74 | /* Top of Lower Usable DRAM */ |
| 75 | tor = (pci_read_config16(dev, D0F0_TOLUD) & 0xfff0) << 16; |
| 76 | |
| 77 | /* Graphics memory comes next */ |
| 78 | const u32 ggc = pci_read_config16(dev, D0F0_GGC); |
| 79 | if (!(ggc & 2)) { |
| 80 | /* Graphics memory */ |
| 81 | tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10; |
| 82 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 83 | tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10; |
| 84 | } |
| 85 | return tor; |
| 86 | } |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 87 | |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 88 | /* Depending of UMA and TSEG configuration, TSEG might start at any |
| 89 | * 1 MiB aligment. As this may cause very greedy MTRR setup, push |
| 90 | * CBMEM top downwards to 4 MiB boundary. |
| 91 | */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 92 | void *cbmem_top(void) |
| 93 | { |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 94 | uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB); |
| 95 | return (void *) top_of_ram; |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 96 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 97 | |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 98 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
| 99 | |
| 100 | /* setup_stack_and_mtrrs() determines the stack to use after |
| 101 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 102 | void *setup_stack_and_mtrrs(void) |
| 103 | { |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 104 | struct postcar_frame pcf; |
| 105 | uintptr_t top_of_ram; |
| 106 | |
| 107 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 108 | die("Unable to initialize postcar frame.\n"); |
| 109 | |
| 110 | /* Cache the ROM as WP just below 4GiB. */ |
| 111 | postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, |
| 112 | MTRR_TYPE_WRPROT); |
| 113 | |
| 114 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 115 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 116 | |
| 117 | /* Cache two separate 4 MiB regions below the top of ram, this |
| 118 | * satisfies MTRR alignment requirements. If you modify this to |
| 119 | * cover TSEG, make sure UMA region is not set with WRBACK as it |
| 120 | * causes hard-to-recover boot failures. |
| 121 | */ |
| 122 | top_of_ram = (uintptr_t)cbmem_top(); |
| 123 | postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); |
| 124 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); |
| 125 | |
| 126 | /* Save the number of MTRRs to setup. Return the stack location |
| 127 | * pointing to the number of MTRRs. |
| 128 | */ |
| 129 | return postcar_commit_mtrrs(&pcf); |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 130 | } |