Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | static void setup_mb_resource_map(void) |
| 19 | { |
| 20 | static const unsigned int register_values[] = { |
| 21 | /* Careful set limit registers before base registers which contain the enables */ |
| 22 | /* DRAM Limit i Registers |
| 23 | * F1:0x44 i = 0 |
| 24 | * F1:0x4C i = 1 |
| 25 | * F1:0x54 i = 2 |
| 26 | * F1:0x5C i = 3 |
| 27 | * F1:0x64 i = 4 |
| 28 | * F1:0x6C i = 5 |
| 29 | * F1:0x74 i = 6 |
| 30 | * F1:0x7C i = 7 |
| 31 | * [ 2: 0] Destination Node ID |
| 32 | * 000 = Node 0 |
| 33 | * 001 = Node 1 |
| 34 | * 010 = Node 2 |
| 35 | * 011 = Node 3 |
| 36 | * 100 = Node 4 |
| 37 | * 101 = Node 5 |
| 38 | * 110 = Node 6 |
| 39 | * 111 = Node 7 |
| 40 | * [ 7: 3] Reserved |
| 41 | * [10: 8] Interleave select |
| 42 | * specifies the values of A[14:12] to use with interleave enable. |
| 43 | * [15:11] Reserved |
| 44 | * [31:16] DRAM Limit Address i Bits 39-24 |
| 45 | * This field defines the upper address bits of a 40 bit address |
| 46 | * that define the end of the DRAM region. |
| 47 | */ |
| 48 | PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, |
| 49 | PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, |
| 50 | PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, |
| 51 | PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, |
| 52 | PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, |
| 53 | PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, |
| 54 | PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, |
| 55 | PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, |
| 56 | |
| 57 | /* DRAM Base i Registers |
| 58 | * F1:0x40 i = 0 |
| 59 | * F1:0x48 i = 1 |
| 60 | * F1:0x50 i = 2 |
| 61 | * F1:0x58 i = 3 |
| 62 | * F1:0x60 i = 4 |
| 63 | * F1:0x68 i = 5 |
| 64 | * F1:0x70 i = 6 |
| 65 | * F1:0x78 i = 7 |
| 66 | * [ 0: 0] Read Enable |
| 67 | * 0 = Reads Disabled |
| 68 | * 1 = Reads Enabled |
| 69 | * [ 1: 1] Write Enable |
| 70 | * 0 = Writes Disabled |
| 71 | * 1 = Writes Enabled |
| 72 | * [ 7: 2] Reserved |
| 73 | * [10: 8] Interleave Enable |
| 74 | * 000 = No interleave |
| 75 | * 001 = Interleave on A[12] (2 nodes) |
| 76 | * 010 = reserved |
| 77 | * 011 = Interleave on A[12] and A[14] (4 nodes) |
| 78 | * 100 = reserved |
| 79 | * 101 = reserved |
| 80 | * 110 = reserved |
| 81 | * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) |
| 82 | * [15:11] Reserved |
| 83 | * [13:16] DRAM Base Address i Bits 39-24 |
| 84 | * This field defines the upper address bits of a 40-bit address |
| 85 | * that define the start of the DRAM region. |
| 86 | */ |
| 87 | PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, |
| 88 | PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, |
| 89 | PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, |
| 90 | PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, |
| 91 | PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, |
| 92 | PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, |
| 93 | PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, |
| 94 | PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, |
| 95 | |
| 96 | /* Memory-Mapped I/O Limit i Registers |
| 97 | * F1:0x84 i = 0 |
| 98 | * F1:0x8C i = 1 |
| 99 | * F1:0x94 i = 2 |
| 100 | * F1:0x9C i = 3 |
| 101 | * F1:0xA4 i = 4 |
| 102 | * F1:0xAC i = 5 |
| 103 | * F1:0xB4 i = 6 |
| 104 | * F1:0xBC i = 7 |
| 105 | * [ 2: 0] Destination Node ID |
| 106 | * 000 = Node 0 |
| 107 | * 001 = Node 1 |
| 108 | * 010 = Node 2 |
| 109 | * 011 = Node 3 |
| 110 | * 100 = Node 4 |
| 111 | * 101 = Node 5 |
| 112 | * 110 = Node 6 |
| 113 | * 111 = Node 7 |
| 114 | * [ 3: 3] Reserved |
| 115 | * [ 5: 4] Destination Link ID |
| 116 | * 00 = Link 0 |
| 117 | * 01 = Link 1 |
| 118 | * 10 = Link 2 |
| 119 | * 11 = Reserved |
| 120 | * [ 6: 6] Reserved |
| 121 | * [ 7: 7] Non-Posted |
| 122 | * 0 = CPU writes may be posted |
| 123 | * 1 = CPU writes must be non-posted |
| 124 | * [31: 8] Memory-Mapped I/O Limit Address i (39-16) |
| 125 | * This field defines the upp adddress bits of a 40-bit address that |
| 126 | * defines the end of a memory-mapped I/O region n |
| 127 | */ |
| 128 | PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, |
| 129 | PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, |
| 130 | PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, |
| 131 | PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, |
| 132 | PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, |
| 133 | PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, |
| 134 | PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, |
| 135 | // PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, |
| 136 | |
| 137 | /* Memory-Mapped I/O Base i Registers |
| 138 | * F1:0x80 i = 0 |
| 139 | * F1:0x88 i = 1 |
| 140 | * F1:0x90 i = 2 |
| 141 | * F1:0x98 i = 3 |
| 142 | * F1:0xA0 i = 4 |
| 143 | * F1:0xA8 i = 5 |
| 144 | * F1:0xB0 i = 6 |
| 145 | * F1:0xB8 i = 7 |
| 146 | * [ 0: 0] Read Enable |
| 147 | * 0 = Reads disabled |
| 148 | * 1 = Reads Enabled |
| 149 | * [ 1: 1] Write Enable |
| 150 | * 0 = Writes disabled |
| 151 | * 1 = Writes Enabled |
| 152 | * [ 2: 2] Cpu Disable |
| 153 | * 0 = Cpu can use this I/O range |
| 154 | * 1 = Cpu requests do not use this I/O range |
| 155 | * [ 3: 3] Lock |
| 156 | * 0 = base/limit registers i are read/write |
| 157 | * 1 = base/limit registers i are read-only |
| 158 | * [ 7: 4] Reserved |
| 159 | * [31: 8] Memory-Mapped I/O Base Address i (39-16) |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 160 | * This field defines the upper address bits of a 40bit address |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 161 | * that defines the start of memory-mapped I/O region i |
| 162 | */ |
| 163 | PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, |
| 164 | PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, |
| 165 | PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, |
| 166 | PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, |
| 167 | PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, |
| 168 | PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, |
| 169 | PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, |
| 170 | // PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, |
| 171 | |
| 172 | /* PCI I/O Limit i Registers |
| 173 | * F1:0xC4 i = 0 |
| 174 | * F1:0xCC i = 1 |
| 175 | * F1:0xD4 i = 2 |
| 176 | * F1:0xDC i = 3 |
| 177 | * [ 2: 0] Destination Node ID |
| 178 | * 000 = Node 0 |
| 179 | * 001 = Node 1 |
| 180 | * 010 = Node 2 |
| 181 | * 011 = Node 3 |
| 182 | * 100 = Node 4 |
| 183 | * 101 = Node 5 |
| 184 | * 110 = Node 6 |
| 185 | * 111 = Node 7 |
| 186 | * [ 3: 3] Reserved |
| 187 | * [ 5: 4] Destination Link ID |
| 188 | * 00 = Link 0 |
| 189 | * 01 = Link 1 |
| 190 | * 10 = Link 2 |
| 191 | * 11 = reserved |
| 192 | * [11: 6] Reserved |
| 193 | * [24:12] PCI I/O Limit Address i |
| 194 | * This field defines the end of PCI I/O region n |
| 195 | * [31:25] Reserved |
| 196 | */ |
| 197 | // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 198 | PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 199 | PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, |
| 200 | PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, |
| 201 | |
| 202 | /* PCI I/O Base i Registers |
| 203 | * F1:0xC0 i = 0 |
| 204 | * F1:0xC8 i = 1 |
| 205 | * F1:0xD0 i = 2 |
| 206 | * F1:0xD8 i = 3 |
| 207 | * [ 0: 0] Read Enable |
| 208 | * 0 = Reads Disabled |
| 209 | * 1 = Reads Enabled |
| 210 | * [ 1: 1] Write Enable |
| 211 | * 0 = Writes Disabled |
| 212 | * 1 = Writes Enabled |
| 213 | * [ 3: 2] Reserved |
| 214 | * [ 4: 4] VGA Enable |
| 215 | * 0 = VGA matches Disabled |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 216 | * 1 = matches all address < 64K and where A[9:0] is in the |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 217 | * range 3B0-3BB or 3C0-3DF independen of the base & limit registers |
| 218 | * [ 5: 5] ISA Enable |
| 219 | * 0 = ISA matches Disabled |
| 220 | * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block |
| 221 | * from matching agains this base/limit pair |
| 222 | * [11: 6] Reserved |
| 223 | * [24:12] PCI I/O Base i |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 224 | * This field defines the start of PCI I/O region n |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 225 | * [31:25] Reserved |
| 226 | */ |
| 227 | // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, |
| 228 | PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, |
| 229 | PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, |
| 230 | PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, |
| 231 | |
| 232 | /* Config Base and Limit i Registers |
| 233 | * F1:0xE0 i = 0 |
| 234 | * F1:0xE4 i = 1 |
| 235 | * F1:0xE8 i = 2 |
| 236 | * F1:0xEC i = 3 |
| 237 | * [ 0: 0] Read Enable |
| 238 | * 0 = Reads Disabled |
| 239 | * 1 = Reads Enabled |
| 240 | * [ 1: 1] Write Enable |
| 241 | * 0 = Writes Disabled |
| 242 | * 1 = Writes Enabled |
| 243 | * [ 2: 2] Device Number Compare Enable |
| 244 | * 0 = The ranges are based on bus number |
| 245 | * 1 = The ranges are ranges of devices on bus 0 |
| 246 | * [ 3: 3] Reserved |
| 247 | * [ 6: 4] Destination Node |
| 248 | * 000 = Node 0 |
| 249 | * 001 = Node 1 |
| 250 | * 010 = Node 2 |
| 251 | * 011 = Node 3 |
| 252 | * 100 = Node 4 |
| 253 | * 101 = Node 5 |
| 254 | * 110 = Node 6 |
| 255 | * 111 = Node 7 |
| 256 | * [ 7: 7] Reserved |
| 257 | * [ 9: 8] Destination Link |
| 258 | * 00 = Link 0 |
| 259 | * 01 = Link 1 |
| 260 | * 10 = Link 2 |
| 261 | * 11 - Reserved |
| 262 | * [15:10] Reserved |
| 263 | * [23:16] Bus Number Base i |
| 264 | * This field defines the lowest bus number in configuration region i |
| 265 | * [31:24] Bus Number Limit i |
| 266 | * This field defines the highest bus number in configuration region i |
| 267 | */ |
Elyes HAOUAS | 8ab989e | 2016-07-30 17:46:17 +0200 | [diff] [blame^] | 268 | // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */ |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 269 | PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 270 | PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 271 | PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 272 | |
| 273 | }; |
| 274 | |
| 275 | int max; |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 276 | max = ARRAY_SIZE(register_values); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 277 | setup_resource_map(register_values, max); |
| 278 | } |